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https://github.com/c64scene-ar/llvm-6502.git
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23dc769a9b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8
124 lines
3.3 KiB
TableGen
124 lines
3.3 KiB
TableGen
//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction defs that are common to all hw codegen
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// targets.
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//
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//===----------------------------------------------------------------------===//
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class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
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field bits<16> AMDILOp = 0;
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field bits<3> Gen = 0;
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let Namespace = "AMDGPU";
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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let Itinerary = NullALU;
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let TSFlags{42-40} = Gen;
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let TSFlags{63-48} = AMDILOp;
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}
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class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
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: AMDGPUInst<outs, ins, asm, pattern> {
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field bits<32> Inst = 0xffffffff;
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}
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class Constants {
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int TWO_PI = 0x40c90fdb;
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int PI = 0x40490fdb;
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int TWO_PI_INV = 0x3e22f983;
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}
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def CONST : Constants;
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def FP_ZERO : PatLeaf <
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(fpimm),
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[{return N->getValueAPF().isZero();}]
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>;
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def FP_ONE : PatLeaf <
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(fpimm),
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[{return N->isExactlyValue(1.0);}]
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>;
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let isCodeGenOnly = 1, isPseudo = 1, usesCustomInserter = 1 in {
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class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"CLAMP $dst, $src0",
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[(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
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>;
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class FABS <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FABS $dst, $src0",
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[(set rc:$dst, (fabs rc:$src0))]
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>;
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class FNEG <RegisterClass rc> : AMDGPUShaderInst <
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(outs rc:$dst),
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(ins rc:$src0),
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"FNEG $dst, $src0",
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[(set rc:$dst, (fneg rc:$src0))]
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>;
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} // End isCodeGenOnly = 1, isPseudo = 1, hasCustomInserter = 1
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/* Generic helper patterns for intrinsics */
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/* -------------------------------------- */
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class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul,
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RegisterClass rc> : Pat <
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(int_AMDGPU_pow rc:$src0, rc:$src1),
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(exp_ieee (mul rc:$src1, (log_ieee rc:$src0)))
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>;
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/* Other helper patterns */
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/* --------------------- */
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/* Extract element pattern */
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class Extract_Element <ValueType sub_type, ValueType vec_type,
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RegisterClass vec_class, int sub_idx,
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SubRegIndex sub_reg>: Pat<
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(sub_type (vector_extract (vec_type vec_class:$src), sub_idx)),
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(EXTRACT_SUBREG vec_class:$src, sub_reg)
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>;
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/* Insert element pattern */
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class Insert_Element <ValueType elem_type, ValueType vec_type,
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RegisterClass elem_class, RegisterClass vec_class,
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int sub_idx, SubRegIndex sub_reg> : Pat <
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(vec_type (vector_insert (vec_type vec_class:$vec),
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(elem_type elem_class:$elem), sub_idx)),
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(INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg)
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>;
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// Vector Build pattern
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class Vector_Build <ValueType vecType, RegisterClass elemClass> : Pat <
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(IL_vbuild elemClass:$src),
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(INSERT_SUBREG (vecType (IMPLICIT_DEF)), elemClass:$src, sel_x)
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>;
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// bitconvert pattern
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class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
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(dt (bitconvert (st rc:$src0))),
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(dt rc:$src0)
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>;
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include "R600Instructions.td"
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include "SIInstrInfo.td"
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