llvm-6502/test/CodeGen
Ulrich Weigand 58fc1f52ce [PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD
The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD
correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD.
This causes some confusion with the asm parser, since VK_PPC_TLSGD
is output as @tlsgd, which is then read back in as VK_TLSGD.

To avoid this confusion, this patch removes the PowerPC-specific
modifiers and uses the generic modifiers throughout.  (The only
drawback is that the generic modifiers are printed in upper case
while the usual convention on PowerPC is to use lower-case modifiers.
But this is just a cosmetic issue.)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-02 21:29:06 +00:00
..
AArch64 AArch64: correct CodeGen of MOVZ/MOVK combinations. 2013-07-01 19:23:10 +00:00
ARM Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst") 2013-07-01 18:37:33 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips [mips] Fix test case to check that mips64 instructions are generated. 2013-07-01 20:18:58 +00:00
MSP430 Really fix the test. Sorry for the breakage... 2013-07-01 19:51:36 +00:00
NVPTX [NVPTX] Add support for module-scope inline asm 2013-07-01 13:00:14 +00:00
PowerPC [PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLD 2013-07-02 21:29:06 +00:00
R600
SI
SPARC
SystemZ [SystemZ] Use DSGFR over DSGR in more cases 2013-07-02 15:40:22 +00:00
Thumb
Thumb2
X86 DAGCombiner: fix use-counting issue when forming zextload 2013-07-02 09:58:53 +00:00
XCore [XCore] Fix instruction selection for zext, mkmsk instructions. 2013-07-02 14:46:34 +00:00