Jim Laskey 242f2557cc Should be using flag and not chain. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23572 91177308-0d34-0410-b5e6-96231b3b80d8

2005-09-30 23:43:37 +00:00

..

Alpha

subtarget support for CIX and FIX extentions (the only 2 I care about right now)

2005-09-30 20:24:38 +00:00

CBackend

fix CBackend/2005-09-27-VolatileFuncPtr.ll

2005-09-27 20:52:44 +00:00

IA64

these registers don't belong to any register classes, so don't mark them

2005-09-30 06:42:24 +00:00

PowerPC

Should be using flag and not chain.

2005-09-30 23:43:37 +00:00

Skeleton

CR registers are not used by this "target"

2005-09-30 06:43:58 +00:00

Sparc

Pass extra regclasses into spilling code

2005-09-30 01:29:42 +00:00

SparcV8

Pass extra regclasses into spilling code

2005-09-30 01:29:42 +00:00

SparcV9

Rename MRegisterDesc -> TargetRegisterDesc for consistency

2005-09-30 17:49:27 +00:00

X86

simplify this code using the new regclass info passed in

2005-09-30 17:12:38 +00:00

Makefile

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MRegisterInfo.cpp

Rename MRegisterDesc -> TargetRegisterDesc for consistency

2005-09-30 17:49:27 +00:00

SubtargetFeature.cpp

Print:

2005-09-07 05:44:14 +00:00

Target.td

Now that self referential classes are supported, get rid of a work-around.

2005-09-30 04:13:23 +00:00

TargetData.cpp

Update to use the new MathExtras.h support for log2 computation.

2005-08-02 19:26:06 +00:00

TargetFrameInfo.cpp

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TargetInstrInfo.cpp

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TargetMachine.cpp

Remove the X86 and PowerPC Simple instruction selectors; their time has

2005-08-18 23:53:15 +00:00

TargetMachineRegistry.cpp

1. Use SubtargetFeatures in llc/lli.

2005-09-01 21:38:21 +00:00

TargetSchedInfo.cpp

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TargetSubtarget.cpp

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