mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-24 09:29:42 +00:00
58f8a138a9
Summary: This patch first change the register that holds local address for stack frame to %SPL. Then the new NVPTXPeephole pass will try to scan the following pattern %vreg0<def> = LEA_ADDRi64 <fi#0>, 4 %vreg1<def> = cvta_to_local %vreg0 and transform it into %vreg1<def> = LEA_ADDRi64 %VRFrameLocal, 4 Patched by Xuetian Weng Test Plan: test/CodeGen/NVPTX/local-stack-frame.ll Reviewers: jholewinski, jingyue Reviewed By: jingyue Subscribers: eliben, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D10549 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240587 91177308-0d34-0410-b5e6-96231b3b80d8
42 lines
1.1 KiB
CMake
42 lines
1.1 KiB
CMake
set(LLVM_TARGET_DEFINITIONS NVPTX.td)
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tablegen(LLVM NVPTXGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM NVPTXGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM NVPTXGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM NVPTXGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM NVPTXGenSubtargetInfo.inc -gen-subtarget)
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add_public_tablegen_target(NVPTXCommonTableGen)
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set(NVPTXCodeGen_sources
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NVPTXAllocaHoisting.cpp
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NVPTXAsmPrinter.cpp
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NVPTXAssignValidGlobalNames.cpp
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NVPTXFavorNonGenericAddrSpaces.cpp
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NVPTXFrameLowering.cpp
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NVPTXGenericToNVVM.cpp
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NVPTXISelDAGToDAG.cpp
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NVPTXISelLowering.cpp
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NVPTXImageOptimizer.cpp
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NVPTXInstrInfo.cpp
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NVPTXLowerAggrCopies.cpp
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NVPTXLowerKernelArgs.cpp
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NVPTXLowerAlloca.cpp
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NVPTXPeephole.cpp
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NVPTXMCExpr.cpp
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NVPTXPrologEpilogPass.cpp
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NVPTXRegisterInfo.cpp
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NVPTXReplaceImageHandles.cpp
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NVPTXSubtarget.cpp
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NVPTXTargetMachine.cpp
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NVPTXTargetTransformInfo.cpp
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NVPTXUtilities.cpp
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NVVMReflect.cpp
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)
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add_llvm_target(NVPTXCodeGen ${NVPTXCodeGen_sources})
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add_subdirectory(TargetInfo)
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add_subdirectory(InstPrinter)
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add_subdirectory(MCTargetDesc)
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