mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0f5f7c0c1b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227321 91177308-0d34-0410-b5e6-96231b3b80d8
137 lines
3.1 KiB
LLVM
137 lines
3.1 KiB
LLVM
; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
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; Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU
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; Add
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declare i32 @llvm.hexagon.A2.addi(i32, i32)
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define i32 @A2_addi(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.addi(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: r0 = add(r0, #0)
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declare i32 @llvm.hexagon.A2.add(i32, i32)
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define i32 @A2_add(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.add(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = add(r0, r1)
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declare i32 @llvm.hexagon.A2.addsat(i32, i32)
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define i32 @A2_addsat(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.addsat(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = add(r0, r1):sat
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; Logical operations
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declare i32 @llvm.hexagon.A2.and(i32, i32)
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define i32 @A2_and(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.and(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = and(r0, r1)
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declare i32 @llvm.hexagon.A2.or(i32, i32)
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define i32 @A2_or(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.or(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = or(r0, r1)
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declare i32 @llvm.hexagon.A2.xor(i32, i32)
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define i32 @A2_xor(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.xor(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = xor(r0, r1)
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declare i32 @llvm.hexagon.A4.andn(i32, i32)
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define i32 @A4_andn(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.andn(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = and(r0, ~r1)
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declare i32 @llvm.hexagon.A4.orn(i32, i32)
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define i32 @A4_orn(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A4.orn(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = or(r0, ~r1)
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; Nop
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declare void @llvm.hexagon.A2.nop()
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define void @A2_nop(i32 %a, i32 %b) {
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call void @llvm.hexagon.A2.nop()
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ret void
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}
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; CHECK: nop
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; Subtract
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declare i32 @llvm.hexagon.A2.sub(i32, i32)
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define i32 @A2_sub(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.sub(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = sub(r0, r1)
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declare i32 @llvm.hexagon.A2.subsat(i32, i32)
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define i32 @A2_subsat(i32 %a, i32 %b) {
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%z = call i32 @llvm.hexagon.A2.subsat(i32 %a, i32 %b)
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ret i32 %z
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}
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; CHECK: r0 = sub(r0, r1):sat
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; Sign extend
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declare i32 @llvm.hexagon.A2.sxtb(i32)
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define i32 @A2_sxtb(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.sxtb(i32 %a)
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ret i32 %z
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}
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; CHECK: r0 = sxtb(r0)
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declare i32 @llvm.hexagon.A2.sxth(i32)
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define i32 @A2_sxth(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.sxth(i32 %a)
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ret i32 %z
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}
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; CHECK: r0 = sxth(r0)
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; Transfer immediate
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declare i32 @llvm.hexagon.A2.tfril(i32, i32)
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define i32 @A2_tfril(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.tfril(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: r0.l = #0
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declare i32 @llvm.hexagon.A2.tfrih(i32, i32)
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define i32 @A2_tfrih(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.tfrih(i32 %a, i32 0)
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ret i32 %z
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}
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; CHECK: r0.h = #0
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declare i32 @llvm.hexagon.A2.tfrsi(i32)
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define i32 @A2_tfrsi() {
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%z = call i32 @llvm.hexagon.A2.tfrsi(i32 0)
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ret i32 %z
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}
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; CHECK: r0 = #0
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; Transfer register
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declare i32 @llvm.hexagon.A2.tfr(i32)
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define i32 @A2_tfr(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.tfr(i32 %a)
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ret i32 %z
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}
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; CHECK: r0 = r0
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; Zero extend
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declare i32 @llvm.hexagon.A2.zxth(i32)
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define i32 @A2_zxth(i32 %a) {
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%z = call i32 @llvm.hexagon.A2.zxth(i32 %a)
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ret i32 %z
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}
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; CHECK: r0 = zxth(r0)
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