mirror of
https://github.com/c64scene-ar/llvm-6502.git
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b7653df085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2180 91177308-0d34-0410-b5e6-96231b3b80d8
292 lines
10 KiB
C++
292 lines
10 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// Sparc.cpp
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//
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// Purpose:
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//
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// History:
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// 7/15/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "SparcInternals.h"
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#include "llvm/Target/Sparc.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineCodeForMethod.h"
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#include "llvm/CodeGen/RegisterAllocation.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Function.h"
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#include "llvm/BasicBlock.h"
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#include "llvm/PassManager.h"
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#include <iostream>
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using std::cerr;
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// Build the MachineInstruction Description Array...
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const MachineInstrDescriptor SparcMachineInstrDesc[] = {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS },
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#include "SparcInstr.def"
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};
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//----------------------------------------------------------------------------
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// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
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//----------------------------------------------------------------------------
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//
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TargetMachine *allocateSparcTargetMachine() { return new UltraSparc(); }
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//---------------------------------------------------------------------------
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// class InsertPrologEpilogCode
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//
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// Insert SAVE/RESTORE instructions for the function
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//
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// Insert prolog code at the unique function entry point.
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// Insert epilog code at each function exit point.
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// InsertPrologEpilog invokes these only if the function is not compiled
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// with the leaf function optimization.
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//
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//---------------------------------------------------------------------------
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static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR];
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class InsertPrologEpilogCode : public MethodPass {
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TargetMachine &Target;
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public:
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inline InsertPrologEpilogCode(TargetMachine &T) : Target(T) {}
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bool runOnMethod(Function *F) {
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MachineCodeForMethod &mcodeInfo = MachineCodeForMethod::get(F);
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if (!mcodeInfo.isCompiledAsLeafMethod()) {
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InsertPrologCode(F);
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InsertEpilogCode(F);
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}
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return false;
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}
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void InsertPrologCode(Function *F);
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void InsertEpilogCode(Function *F);
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};
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void InsertPrologEpilogCode::InsertPrologCode(Function *F)
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{
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BasicBlock *entryBB = F->getEntryNode();
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unsigned N = GetInstructionsForProlog(entryBB, Target, minstrVec);
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assert(N <= MAX_INSTR_PER_VMINSTR);
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MachineCodeForBasicBlock& bbMvec = entryBB->getMachineInstrVec();
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bbMvec.insert(bbMvec.begin(), minstrVec, minstrVec+N);
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}
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void InsertPrologEpilogCode::InsertEpilogCode(Function *F)
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{
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for (Function::iterator I = F->begin(), E = F->end(); I != E; ++I) {
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Instruction *TermInst = (Instruction*)(*I)->getTerminator();
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if (TermInst->getOpcode() == Instruction::Ret)
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{
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BasicBlock* exitBB = *I;
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unsigned N = GetInstructionsForEpilog(exitBB, Target, minstrVec);
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MachineCodeForBasicBlock& bbMvec = exitBB->getMachineInstrVec();
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MachineCodeForInstruction &termMvec =
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MachineCodeForInstruction::get(TermInst);
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// Remove the NOPs in the delay slots of the return instruction
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const MachineInstrInfo &mii = Target.getInstrInfo();
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unsigned numNOPs = 0;
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while (termMvec.back()->getOpCode() == NOP)
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{
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assert( termMvec.back() == bbMvec.back());
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termMvec.pop_back();
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bbMvec.pop_back();
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++numNOPs;
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}
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assert(termMvec.back() == bbMvec.back());
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// Check that we found the right number of NOPs and have the right
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// number of instructions to replace them.
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unsigned ndelays = mii.getNumDelaySlots(termMvec.back()->getOpCode());
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assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
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assert(N == ndelays && "Cannot use epilog code for delay slots?");
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// Append the epilog code to the end of the basic block.
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bbMvec.insert(bbMvec.end(), minstrVec, minstrVec+N);
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}
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}
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}
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//---------------------------------------------------------------------------
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// class UltraSparcFrameInfo
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//
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// Purpose:
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// Interface to stack frame layout info for the UltraSPARC.
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// Starting offsets for each area of the stack frame are aligned at
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// a multiple of getStackFrameSizeAlignment().
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//---------------------------------------------------------------------------
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int
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UltraSparcFrameInfo::getFirstAutomaticVarOffset(MachineCodeForMethod& ,
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bool& pos) const
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{
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pos = false; // static stack area grows downwards
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return StaticAreaOffsetFromFP;
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}
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int
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UltraSparcFrameInfo::getRegSpillAreaOffset(MachineCodeForMethod& mcInfo,
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bool& pos) const
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{
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pos = false; // static stack area grows downwards
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unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize();
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if (int mod = autoVarsSize % getStackFrameSizeAlignment())
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autoVarsSize += (getStackFrameSizeAlignment() - mod);
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return StaticAreaOffsetFromFP - autoVarsSize;
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}
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int
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UltraSparcFrameInfo::getTmpAreaOffset(MachineCodeForMethod& mcInfo,
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bool& pos) const
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{
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pos = false; // static stack area grows downwards
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unsigned int autoVarsSize = mcInfo.getAutomaticVarsSize();
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unsigned int spillAreaSize = mcInfo.getRegSpillsSize();
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int offset = autoVarsSize + spillAreaSize;
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if (int mod = offset % getStackFrameSizeAlignment())
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offset += (getStackFrameSizeAlignment() - mod);
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return StaticAreaOffsetFromFP - offset;
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}
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int
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UltraSparcFrameInfo::getDynamicAreaOffset(MachineCodeForMethod& mcInfo,
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bool& pos) const
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{
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// Dynamic stack area grows downwards starting at top of opt-args area.
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// The opt-args, required-args, and register-save areas are empty except
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// during calls and traps, so they are shifted downwards on each
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// dynamic-size alloca.
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pos = false;
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unsigned int optArgsSize = mcInfo.getMaxOptionalArgsSize();
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int offset = optArgsSize + FirstOptionalOutgoingArgOffsetFromSP;
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assert((offset - OFFSET) % getStackFrameSizeAlignment() == 0);
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return offset;
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}
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//---------------------------------------------------------------------------
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// class UltraSparcMachine
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//
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// Purpose:
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// Primary interface to machine description for the UltraSPARC.
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// Primarily just initializes machine-dependent parameters in
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// class TargetMachine, and creates machine-dependent subclasses
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// for classes such as MachineInstrInfo.
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//
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//---------------------------------------------------------------------------
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UltraSparc::UltraSparc()
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: TargetMachine("UltraSparc-Native"),
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instrInfo(*this),
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schedInfo(*this),
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regInfo(*this),
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frameInfo(*this),
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cacheInfo(*this)
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{
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optSizeForSubWordData = 4;
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minMemOpWordSize = 8;
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maxAtomicMemOpWordSize = 8;
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}
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//===---------------------------------------------------------------------===//
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// GenerateCodeForTarget Pass
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//
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// Native code generation for a specified target.
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//===---------------------------------------------------------------------===//
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class ConstructMachineCodeForFunction : public MethodPass {
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TargetMachine &Target;
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public:
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inline ConstructMachineCodeForFunction(TargetMachine &T) : Target(T) {}
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bool runOnMethod(Function *F) {
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MachineCodeForMethod::construct(F, Target);
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return false;
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}
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};
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class InstructionSelection : public MethodPass {
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TargetMachine &Target;
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public:
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inline InstructionSelection(TargetMachine &T) : Target(T) {}
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bool runOnMethod(Function *F) {
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if (SelectInstructionsForMethod(F, Target)) {
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cerr << "Instr selection failed for function " << F->getName() << "\n";
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abort();
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}
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return false;
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}
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};
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struct FreeMachineCodeForFunction : public MethodPass {
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static void freeMachineCode(Instruction *I) {
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MachineCodeForInstruction::destroy(I);
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}
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bool runOnMethod(Function *F) {
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for (Function::iterator FI = F->begin(), FE = F->end(); FI != FE; ++FI)
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for (BasicBlock::iterator I = (*FI)->begin(), E = (*FI)->end();
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I != E; ++I)
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MachineCodeForInstruction::get(*I).dropAllReferences();
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for (Function::iterator FI = F->begin(), FE = F->end(); FI != FE; ++FI)
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for (BasicBlock::iterator I = (*FI)->begin(), E = (*FI)->end();
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I != E; ++I)
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freeMachineCode(*I);
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return false;
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}
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};
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// addPassesToEmitAssembly - This method controls the entire code generation
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// process for the ultra sparc.
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//
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void UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) {
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// Construct and initialize the MachineCodeForMethod object for this fn.
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PM.add(new ConstructMachineCodeForFunction(*this));
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PM.add(new InstructionSelection(*this));
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PM.add(createInstructionSchedulingWithSSAPass(*this));
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PM.add(getRegisterAllocator(*this));
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//PM.add(new OptimizeLeafProcedures());
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//PM.add(new DeleteFallThroughBranches());
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//PM.add(new RemoveChainedBranches()); // should be folded with previous
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//PM.add(new RemoveRedundantOps()); // operations with %g0, NOP, etc.
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PM.add(new InsertPrologEpilogCode(*this));
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// Output assembly language to the .s file. Assembly emission is split into
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// two parts: Function output and Global value output. This is because
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// function output is pipelined with all of the rest of code generation stuff,
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// allowing machine code representations for functions to be free'd after the
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// function has been emitted.
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//
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PM.add(getMethodAsmPrinterPass(PM, Out));
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PM.add(new FreeMachineCodeForFunction()); // Free stuff no longer needed
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// Emit Module level assembly after all of the functions have been processed.
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PM.add(getModuleAsmPrinterPass(PM, Out));
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// Emit bytecode to the sparc assembly file into its special section next
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PM.add(getEmitBytecodeToAsmPass(Out));
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}
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