Matt Arsenault 24463c7df7 R600/SI: Remove redundant setting of instruction bits ... These are all set on the instruction base classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220091 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-17 21:13:11 +00:00
..
InstPrinter	R600/SI: Change how DS offsets are printed	2014-10-10 22:16:07 +00:00
MCTargetDesc	Simplify handling of --noexecstack by using getNonexecutableStackSection.	2014-10-15 16:12:52 +00:00
TargetInfo
AMDGPU.h	R600/SI: Add load / store machine optimizer pass.	2014-10-10 22:01:59 +00:00
AMDGPU.td	R600/SI: Add load / store machine optimizer pass.	2014-10-10 22:01:59 +00:00
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPUInstructions.td
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp	R600/SI: Remove SI_BUFFER_RSRC pseudo	2014-10-17 17:42:56 +00:00
AMDGPUISelLowering.cpp	R600: Fix nonsensical implementation of computeKnownBits for BFE	2014-10-16 20:07:40 +00:00
AMDGPUISelLowering.h	R600: Remove dead function	2014-10-16 00:08:09 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h	Reapply "R600: Add new intrinsic to read work dimensions"	2014-10-14 20:05:26 +00:00
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPUPromoteAlloca.cpp
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp	R600/SI: Add load / store machine optimizer pass.	2014-10-10 22:01:59 +00:00
AMDGPUSubtarget.h	R600/SI: Add load / store machine optimizer pass.	2014-10-10 22:01:59 +00:00
AMDGPUTargetMachine.cpp	R600/SI: Add load / store machine optimizer pass.	2014-10-10 22:01:59 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDILCFGStructurizer.cpp
CaymanInstructions.td
CMakeLists.txt	R600/SI: Add load / store machine optimizer pass.	2014-10-10 22:01:59 +00:00
EvergreenInstructions.td
LLVMBuild.txt
Makefile
Processors.td
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp
R600InstrInfo.h
R600Instructions.td	R600: FMA is VecALU only instruction	2014-10-14 18:52:04 +00:00
R600Intrinsics.td
R600ISelLowering.cpp	Reapply "R600: Add new intrinsic to read work dimensions"	2014-10-14 20:05:26 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp	R600/SI: Simplify debug printing	2014-10-17 00:36:20 +00:00
SIFixSGPRLiveRanges.cpp
SIInsertWaits.cpp
SIInstrFormats.td
SIInstrInfo.cpp	Fix typo	2014-10-17 18:02:31 +00:00
SIInstrInfo.h	R600/SI: Fix general commuting breaking src mods	2014-10-17 18:00:43 +00:00
SIInstrInfo.td	R600/SI: Change how DS offsets are printed	2014-10-10 22:16:07 +00:00
SIInstructions.td	R600/SI: Remove redundant setting of instruction bits	2014-10-17 21:13:11 +00:00
SIIntrinsics.td
SIISelLowering.cpp	R600/SI: Remove SI_BUFFER_RSRC pseudo	2014-10-17 17:42:56 +00:00
SIISelLowering.h
SILoadStoreOptimizer.cpp	R600/SI: Match read2/write2 stride 64 versions	2014-10-10 22:12:32 +00:00
SILowerControlFlow.cpp
SILowerI1Copies.cpp
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp
SIRegisterInfo.h
SIRegisterInfo.td
SISchedule.td
SIShrinkInstructions.cpp	R600/SI: Also check for FPImm literal constants	2014-10-17 18:00:50 +00:00
SITypeRewriter.cpp