mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2466c3766d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44597 91177308-0d34-0410-b5e6-96231b3b80d8
615 lines
18 KiB
C++
615 lines
18 KiB
C++
//===-- SPUISelDAGToDAG.cpp - CellSPU -pattern matching inst selector -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by a team from the Computer Systems Research
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// Department at The Aerospace Corporation and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for the Cell SPU,
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// converting from a legalized dag to a SPU-target dag.
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//
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//===----------------------------------------------------------------------===//
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#include "SPU.h"
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#include "SPUTargetMachine.h"
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#include "SPUISelLowering.h"
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#include "SPUHazardRecognizers.h"
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#include "SPUFrameInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Constants.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Compiler.h"
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#include <iostream>
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#include <queue>
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#include <set>
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using namespace llvm;
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namespace {
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//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
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bool
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isI64IntS10Immediate(ConstantSDNode *CN)
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{
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return isS10Constant(CN->getValue());
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}
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//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
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bool
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isI32IntS10Immediate(ConstantSDNode *CN)
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{
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return isS10Constant((int) CN->getValue());
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}
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#if 0
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//! SDNode predicate for sign-extended, 10-bit immediate values
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bool
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isI32IntS10Immediate(SDNode *N)
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{
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return (N->getOpcode() == ISD::Constant
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&& isI32IntS10Immediate(cast<ConstantSDNode>(N)));
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}
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#endif
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//! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
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bool
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isI16IntS10Immediate(ConstantSDNode *CN)
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{
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return isS10Constant((short) CN->getValue());
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}
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//! SDNode predicate for i16 sign-extended, 10-bit immediate values
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bool
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isI16IntS10Immediate(SDNode *N)
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{
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return (N->getOpcode() == ISD::Constant
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&& isI16IntS10Immediate(cast<ConstantSDNode>(N)));
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}
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//! ConstantSDNode predicate for signed 16-bit values
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/*!
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\arg CN The constant SelectionDAG node holding the value
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\arg Imm The returned 16-bit value, if returning true
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This predicate tests the value in \a CN to see whether it can be
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represented as a 16-bit, sign-extended quantity. Returns true if
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this is the case.
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*/
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bool
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isIntS16Immediate(ConstantSDNode *CN, short &Imm)
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{
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MVT::ValueType vt = CN->getValueType(0);
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Imm = (short) CN->getValue();
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if (vt >= MVT::i1 && vt <= MVT::i16) {
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return true;
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} else if (vt == MVT::i32) {
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int32_t i_val = (int32_t) CN->getValue();
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short s_val = (short) i_val;
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return i_val == s_val;
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} else {
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int64_t i_val = (int64_t) CN->getValue();
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short s_val = (short) i_val;
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return i_val == s_val;
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}
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return false;
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}
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//! SDNode predicate for signed 16-bit values.
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bool
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isIntS16Immediate(SDNode *N, short &Imm)
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{
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return (N->getOpcode() == ISD::Constant
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&& isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
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}
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//! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
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static bool
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isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
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{
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MVT::ValueType vt = FPN->getValueType(0);
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if (vt == MVT::f32) {
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const APFloat &apf = FPN->getValueAPF();
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float fval = apf.convertToFloat();
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int val = *((int *) &fval);
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int sval = (int) ((val << 16) >> 16);
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Imm = (short) val;
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return val == sval;
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}
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return false;
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}
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//===------------------------------------------------------------------===//
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//! MVT::ValueType to useful stuff structure:
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struct valtype_map_s {
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MVT::ValueType VT;
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unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
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int prefslot_byte; /// Byte offset of the "preferred" slot
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unsigned brcc_eq_ins; /// br_cc equal instruction
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unsigned brcc_neq_ins; /// br_cc not equal instruction
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};
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const valtype_map_s valtype_map[] = {
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{ MVT::i1, 0, 3, 0, 0 },
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{ MVT::i8, 0, 3, 0, 0 },
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{ MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
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{ MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
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{ MVT::i64, SPU::ORIr64, 0, 0, 0 },
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{ MVT::f32, SPU::ORIf32, 0, 0, 0 },
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{ MVT::f64, SPU::ORIf64, 0, 0, 0 }
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};
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const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
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const valtype_map_s *getValueTypeMapEntry(MVT::ValueType VT)
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{
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const valtype_map_s *retval = 0;
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for (size_t i = 0; i < n_valtype_map; ++i) {
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if (valtype_map[i].VT == VT) {
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retval = valtype_map + i;
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break;
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}
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}
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#ifndef NDEBUG
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if (retval == 0) {
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cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
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<< MVT::getValueTypeString(VT)
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<< "\n";
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abort();
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}
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#endif
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return retval;
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}
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}
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//===--------------------------------------------------------------------===//
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/// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
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/// instructions for SelectionDAG operations.
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///
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class SPUDAGToDAGISel :
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public SelectionDAGISel
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{
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SPUTargetMachine &TM;
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SPUTargetLowering &SPUtli;
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unsigned GlobalBaseReg;
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public:
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SPUDAGToDAGISel(SPUTargetMachine &tm) :
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SelectionDAGISel(*tm.getTargetLowering()),
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TM(tm),
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SPUtli(*tm.getTargetLowering())
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{}
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseReg = 0;
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SelectionDAGISel::runOnFunction(Fn);
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return true;
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDOperand getI32Imm(uint32_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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/// getI64Imm - Return a target constant with the specified value, of type
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/// i64.
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inline SDOperand getI64Imm(uint64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i64);
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}
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/// getSmallIPtrImm - Return a target constant of pointer type.
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inline SDOperand getSmallIPtrImm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
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}
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/// Select - Convert the specified operand from a target-independent to a
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/// target-specific node if it hasn't already been changed.
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SDNode *Select(SDOperand Op);
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/// Return true if the address N is a RI7 format address [r+imm]
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bool SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
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SDOperand &Base);
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//! Returns true if the address N is an A-form (local store) address
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bool SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Index);
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//! D-form address predicate
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bool SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Index);
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//! Address predicate if N can be expressed as an indexed [r+r] operation.
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bool SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Index);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
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char ConstraintCode,
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std::vector<SDOperand> &OutOps,
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SelectionDAG &DAG) {
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SDOperand Op0, Op1;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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if (!SelectDFormAddr(Op, Op, Op0, Op1)
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&& !SelectAFormAddr(Op, Op, Op0, Op1))
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SelectXFormAddr(Op, Op, Op0, Op1);
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break;
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case 'o': // offsetable
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if (!SelectDFormAddr(Op, Op, Op0, Op1)
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&& !SelectAFormAddr(Op, Op, Op0, Op1)) {
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Op0 = Op;
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AddToISelQueue(Op0); // r+0.
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Op1 = getSmallIPtrImm(0);
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}
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break;
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case 'v': // not offsetable
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#if 1
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assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
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#else
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SelectAddrIdxOnly(Op, Op, Op0, Op1);
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#endif
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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return "Cell SPU DAG->DAG Pattern Instruction Selection";
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}
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/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
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/// this target when scheduling the DAG.
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virtual HazardRecognizer *CreateTargetHazardRecognizer() {
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const TargetInstrInfo *II = SPUtli.getTargetMachine().getInstrInfo();
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assert(II && "No InstrInfo?");
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return new SPUHazardRecognizer(*II);
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}
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// Include the pieces autogenerated from the target description.
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#include "SPUGenDAGISel.inc"
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};
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void
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SPUDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG)
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{
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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bool
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SPUDAGToDAGISel::SelectDForm2Addr(SDOperand Op, SDOperand N, SDOperand &Disp,
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SDOperand &Base) {
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unsigned Opc = N.getOpcode();
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unsigned VT = N.getValueType();
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MVT::ValueType PtrVT = SPUtli.getPointerTy();
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ConstantSDNode *CN = 0;
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int Imm;
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if (Opc == ISD::ADD) {
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SDOperand Op0 = N.getOperand(0);
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SDOperand Op1 = N.getOperand(1);
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if (Op1.getOpcode() == ISD::Constant ||
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Op1.getOpcode() == ISD::TargetConstant) {
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CN = cast<ConstantSDNode>(Op1);
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Imm = int(CN->getValue());
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if (Imm <= 0xff) {
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Disp = CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
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Base = Op0;
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return true;
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}
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}
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} else if (Opc == ISD::GlobalAddress
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|| Opc == ISD::TargetGlobalAddress
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|| Opc == ISD::Register) {
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// Plain old local store address:
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Disp = CurDAG->getTargetConstant(0, VT);
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Base = N;
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return true;
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} else if (Opc == SPUISD::DFormAddr) {
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// D-Form address: This is pretty straightforward, naturally...
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CN = cast<ConstantSDNode>(N.getOperand(1));
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assert(CN != 0 && "SelectDFormAddr/SPUISD::DForm2Addr expecting constant");
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Imm = unsigned(CN->getValue());
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if (Imm < 0xff) {
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Disp = CurDAG->getTargetConstant(CN->getValue(), PtrVT);
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Base = N.getOperand(0);
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return true;
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}
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}
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return false;
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}
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/*!
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\arg Op The ISD instructio operand
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\arg N The address to be tested
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\arg Base The base address
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\arg Index The base address index
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*/
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bool
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SPUDAGToDAGISel::SelectAFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Index) {
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// These match the addr256k operand type:
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MVT::ValueType PtrVT = SPUtli.getPointerTy();
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MVT::ValueType OffsVT = MVT::i16;
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switch (N.getOpcode()) {
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case ISD::Constant:
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case ISD::TargetConstant: {
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// Loading from a constant address.
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
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int Imm = (int)CN->getValue();
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if (Imm < 0x3ffff && (Imm & 0x3) == 0) {
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Base = CurDAG->getTargetConstant(Imm, PtrVT);
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// Note that this operand will be ignored by the assembly printer...
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Index = CurDAG->getTargetConstant(0, OffsVT);
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return true;
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}
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}
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case ISD::ConstantPool:
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case ISD::TargetConstantPool: {
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// The constant pool address is N. Base is a dummy that will be ignored by
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// the assembly printer.
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Base = N;
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Index = CurDAG->getTargetConstant(0, OffsVT);
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return true;
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}
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case ISD::GlobalAddress:
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case ISD::TargetGlobalAddress: {
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// The global address is N. Base is a dummy that is ignored by the
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// assembly printer.
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Base = N;
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Index = CurDAG->getTargetConstant(0, OffsVT);
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return true;
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}
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}
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return false;
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}
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/*!
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\arg Op The ISD instruction (ignored)
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\arg N The address to be tested
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\arg Base Base address register/pointer
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\arg Index Base address index
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Examine the input address by a base register plus a signed 10-bit
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displacement, [r+I10] (D-form address).
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\return true if \a N is a D-form address with \a Base and \a Index set
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to non-empty SDOperand instances.
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*/
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bool
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SPUDAGToDAGISel::SelectDFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
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SDOperand &Index) {
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unsigned Opc = N.getOpcode();
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unsigned PtrTy = SPUtli.getPointerTy();
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if (Opc == ISD::Register) {
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Base = N;
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Index = CurDAG->getTargetConstant(0, PtrTy);
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return true;
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} else if (Opc == ISD::FrameIndex) {
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// Stack frame index must be less than 512 (divided by 16):
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FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N);
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DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
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<< FI->getIndex() << "\n");
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if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
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Base = CurDAG->getTargetConstant(0, PtrTy);
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Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
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return true;
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}
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} else if (Opc == ISD::ADD) {
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// Generated by getelementptr
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const SDOperand Op0 = N.getOperand(0); // Frame index/base
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const SDOperand Op1 = N.getOperand(1); // Offset within base
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
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// Not a constant?
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if (CN == 0)
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return false;
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int32_t offset = (int32_t) CN->getSignExtended();
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unsigned Opc0 = Op0.getOpcode();
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if ((offset & 0xf) != 0) {
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cerr << "SelectDFormAddr: unaligned offset = " << offset << "\n";
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abort();
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/*NOTREACHED*/
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}
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if (Opc0 == ISD::FrameIndex) {
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FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op0);
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DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
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<< " frame index = " << FI->getIndex() << "\n");
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if (FI->getIndex() < SPUFrameInfo::maxFrameOffset()) {
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Base = CurDAG->getTargetConstant(offset, PtrTy);
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Index = CurDAG->getTargetFrameIndex(FI->getIndex(), PtrTy);
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return true;
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}
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} else if (offset > SPUFrameInfo::minFrameOffset()
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&& offset < SPUFrameInfo::maxFrameOffset()) {
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Base = CurDAG->getTargetConstant(offset, PtrTy);
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if (Opc0 == ISD::GlobalAddress) {
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// Convert global address to target global address
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GlobalAddressSDNode *GV = dyn_cast<GlobalAddressSDNode>(Op0);
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Index = CurDAG->getTargetGlobalAddress(GV->getGlobal(), PtrTy);
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return true;
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} else {
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// Otherwise, just take operand 0
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Index = Op0;
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return true;
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}
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}
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} else if (Opc == SPUISD::DFormAddr) {
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// D-Form address: This is pretty straightforward, naturally...
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ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
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assert(CN != 0 && "SelectDFormAddr/SPUISD::DFormAddr expecting constant");
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Base = CurDAG->getTargetConstant(CN->getValue(), PtrTy);
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Index = N.getOperand(0);
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return true;
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}
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return false;
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}
|
|
|
|
/*!
|
|
\arg Op The ISD instruction operand
|
|
\arg N The address operand
|
|
\arg Base The base pointer operand
|
|
\arg Index The offset/index operand
|
|
|
|
If the address \a N can be expressed as a [r + s10imm] address, returns false.
|
|
Otherwise, creates two operands, Base and Index that will become the [r+r]
|
|
address.
|
|
*/
|
|
bool
|
|
SPUDAGToDAGISel::SelectXFormAddr(SDOperand Op, SDOperand N, SDOperand &Base,
|
|
SDOperand &Index) {
|
|
if (SelectAFormAddr(Op, N, Base, Index)
|
|
|| SelectDFormAddr(Op, N, Base, Index))
|
|
return false;
|
|
|
|
unsigned Opc = N.getOpcode();
|
|
|
|
if (Opc == ISD::ADD) {
|
|
SDOperand N1 = N.getOperand(0);
|
|
SDOperand N2 = N.getOperand(1);
|
|
unsigned N1Opc = N1.getOpcode();
|
|
unsigned N2Opc = N2.getOpcode();
|
|
|
|
if ((N1Opc == SPUISD::Hi && N2Opc == SPUISD::Lo)
|
|
|| (N1Opc == SPUISD::Lo && N2Opc == SPUISD::Hi)) {
|
|
Base = N.getOperand(0);
|
|
Index = N.getOperand(1);
|
|
return true;
|
|
} else {
|
|
cerr << "SelectXFormAddr: Unhandled ADD operands:\n";
|
|
N1.Val->dump();
|
|
cerr << "\n";
|
|
N2.Val->dump();
|
|
cerr << "\n";
|
|
abort();
|
|
/*UNREACHED*/
|
|
}
|
|
} else if (N.getNumOperands() == 2) {
|
|
SDOperand N1 = N.getOperand(0);
|
|
SDOperand N2 = N.getOperand(1);
|
|
unsigned N1Opc = N1.getOpcode();
|
|
unsigned N2Opc = N2.getOpcode();
|
|
|
|
if ((N1Opc == ISD::CopyToReg || N1Opc == ISD::Register)
|
|
&& (N2Opc == ISD::CopyToReg || N2Opc == ISD::Register)) {
|
|
Base = N.getOperand(0);
|
|
Index = N.getOperand(1);
|
|
return true;
|
|
/*UNREACHED*/
|
|
} else {
|
|
cerr << "SelectXFormAddr: 2-operand unhandled operand:\n";
|
|
N.Val->dump();
|
|
cerr << "\n";
|
|
abort();
|
|
/*UNREACHED*/
|
|
}
|
|
} else {
|
|
cerr << "SelectXFormAddr: Unhandled operand type:\n";
|
|
N.Val->dump();
|
|
cerr << "\n";
|
|
abort();
|
|
/*UNREACHED*/
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
//! Convert the operand from a target-independent to a target-specific node
|
|
/*!
|
|
*/
|
|
SDNode *
|
|
SPUDAGToDAGISel::Select(SDOperand Op) {
|
|
SDNode *N = Op.Val;
|
|
unsigned Opc = N->getOpcode();
|
|
|
|
if (Opc >= ISD::BUILTIN_OP_END && Opc < SPUISD::FIRST_NUMBER) {
|
|
return NULL; // Already selected.
|
|
} else if (Opc == ISD::FrameIndex) {
|
|
// Selects to AIr32 FI, 0 which in turn will become AIr32 SP, imm.
|
|
int FI = cast<FrameIndexSDNode>(N)->getIndex();
|
|
SDOperand TFI = CurDAG->getTargetFrameIndex(FI, SPUtli.getPointerTy());
|
|
|
|
DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AI32 TFI, 0\n");
|
|
return CurDAG->SelectNodeTo(N, SPU::AIr32, Op.getValueType(), TFI,
|
|
CurDAG->getTargetConstant(0, MVT::i32));
|
|
} else if (Opc == SPUISD::LDRESULT) {
|
|
// Custom select instructions for LDRESULT
|
|
unsigned VT = N->getValueType(0);
|
|
SDOperand Arg = N->getOperand(0);
|
|
SDOperand Chain = N->getOperand(1);
|
|
SDOperand Zero = CurDAG->getTargetConstant(0, VT);
|
|
SDNode *Result;
|
|
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
|
|
|
|
if (vtm->ldresult_ins == 0) {
|
|
cerr << "LDRESULT for unsupported type: "
|
|
<< MVT::getValueTypeString(VT)
|
|
<< "\n";
|
|
abort();
|
|
} else
|
|
Opc = vtm->ldresult_ins;
|
|
|
|
AddToISelQueue(Arg);
|
|
AddToISelQueue(Zero);
|
|
AddToISelQueue(Chain);
|
|
Result = CurDAG->SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain);
|
|
Chain = SDOperand(Result, 1);
|
|
return Result;
|
|
}
|
|
|
|
return SelectCode(Op);
|
|
}
|
|
|
|
/// createPPCISelDag - This pass converts a legalized DAG into a
|
|
/// SPU-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
|
|
return new SPUDAGToDAGISel(TM);
|
|
}
|