mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44597 91177308-0d34-0410-b5e6-96231b3b80d8
863 lines
29 KiB
C++
863 lines
29 KiB
C++
//===- SPURegisterInfo.cpp - Cell SPU Register Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by a team from the Computer Systems Research
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// Department at The Aerospace Corporation and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "SPU.h"
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#include "SPURegisterInfo.h"
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#include "SPURegisterNames.h"
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#include "SPUInstrBuilder.h"
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#include "SPUSubtarget.h"
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#include "SPUMachineFunction.h"
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#include "SPUFrameInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include <cstdlib>
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#include <iostream>
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using namespace llvm;
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/// getRegisterNumbering - Given the enum value for some register, e.g.
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/// PPC::F14, return the number that it corresponds to (e.g. 14).
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unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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using namespace SPU;
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switch (RegEnum) {
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case SPU::R0: return 0;
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case SPU::R1: return 1;
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case SPU::R2: return 2;
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case SPU::R3: return 3;
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case SPU::R4: return 4;
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case SPU::R5: return 5;
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case SPU::R6: return 6;
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case SPU::R7: return 7;
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case SPU::R8: return 8;
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case SPU::R9: return 9;
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case SPU::R10: return 10;
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case SPU::R11: return 11;
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case SPU::R12: return 12;
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case SPU::R13: return 13;
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case SPU::R14: return 14;
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case SPU::R15: return 15;
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case SPU::R16: return 16;
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case SPU::R17: return 17;
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case SPU::R18: return 18;
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case SPU::R19: return 19;
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case SPU::R20: return 20;
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case SPU::R21: return 21;
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case SPU::R22: return 22;
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case SPU::R23: return 23;
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case SPU::R24: return 24;
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case SPU::R25: return 25;
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case SPU::R26: return 26;
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case SPU::R27: return 27;
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case SPU::R28: return 28;
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case SPU::R29: return 29;
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case SPU::R30: return 30;
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case SPU::R31: return 31;
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case SPU::R32: return 32;
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case SPU::R33: return 33;
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case SPU::R34: return 34;
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case SPU::R35: return 35;
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case SPU::R36: return 36;
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case SPU::R37: return 37;
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case SPU::R38: return 38;
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case SPU::R39: return 39;
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case SPU::R40: return 40;
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case SPU::R41: return 41;
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case SPU::R42: return 42;
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case SPU::R43: return 43;
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case SPU::R44: return 44;
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case SPU::R45: return 45;
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case SPU::R46: return 46;
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case SPU::R47: return 47;
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case SPU::R48: return 48;
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case SPU::R49: return 49;
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case SPU::R50: return 50;
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case SPU::R51: return 51;
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case SPU::R52: return 52;
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case SPU::R53: return 53;
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case SPU::R54: return 54;
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case SPU::R55: return 55;
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case SPU::R56: return 56;
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case SPU::R57: return 57;
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case SPU::R58: return 58;
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case SPU::R59: return 59;
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case SPU::R60: return 60;
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case SPU::R61: return 61;
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case SPU::R62: return 62;
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case SPU::R63: return 63;
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case SPU::R64: return 64;
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case SPU::R65: return 65;
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case SPU::R66: return 66;
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case SPU::R67: return 67;
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case SPU::R68: return 68;
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case SPU::R69: return 69;
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case SPU::R70: return 70;
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case SPU::R71: return 71;
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case SPU::R72: return 72;
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case SPU::R73: return 73;
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case SPU::R74: return 74;
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case SPU::R75: return 75;
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case SPU::R76: return 76;
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case SPU::R77: return 77;
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case SPU::R78: return 78;
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case SPU::R79: return 79;
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case SPU::R80: return 80;
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case SPU::R81: return 81;
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case SPU::R82: return 82;
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case SPU::R83: return 83;
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case SPU::R84: return 84;
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case SPU::R85: return 85;
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case SPU::R86: return 86;
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case SPU::R87: return 87;
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case SPU::R88: return 88;
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case SPU::R89: return 89;
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case SPU::R90: return 90;
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case SPU::R91: return 91;
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case SPU::R92: return 92;
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case SPU::R93: return 93;
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case SPU::R94: return 94;
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case SPU::R95: return 95;
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case SPU::R96: return 96;
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case SPU::R97: return 97;
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case SPU::R98: return 98;
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case SPU::R99: return 99;
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case SPU::R100: return 100;
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case SPU::R101: return 101;
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case SPU::R102: return 102;
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case SPU::R103: return 103;
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case SPU::R104: return 104;
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case SPU::R105: return 105;
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case SPU::R106: return 106;
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case SPU::R107: return 107;
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case SPU::R108: return 108;
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case SPU::R109: return 109;
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case SPU::R110: return 110;
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case SPU::R111: return 111;
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case SPU::R112: return 112;
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case SPU::R113: return 113;
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case SPU::R114: return 114;
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case SPU::R115: return 115;
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case SPU::R116: return 116;
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case SPU::R117: return 117;
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case SPU::R118: return 118;
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case SPU::R119: return 119;
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case SPU::R120: return 120;
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case SPU::R121: return 121;
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case SPU::R122: return 122;
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case SPU::R123: return 123;
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case SPU::R124: return 124;
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case SPU::R125: return 125;
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case SPU::R126: return 126;
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case SPU::R127: return 127;
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default:
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std::cerr << "Unhandled reg in SPURegisterInfo::getRegisterNumbering!\n";
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abort();
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}
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}
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SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
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const TargetInstrInfo &tii) :
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SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
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Subtarget(subtarget),
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TII(tii)
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{
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}
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void
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SPURegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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MachineOpCode opc;
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if (RC == SPU::GPRCRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr128
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: SPU::STQXr128;
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} else if (RC == SPU::R64CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr64
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: SPU::STQXr64;
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} else if (RC == SPU::R64FPRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr64
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: SPU::STQXr64;
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} else if (RC == SPU::R32CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr32
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: SPU::STQXr32;
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} else if (RC == SPU::R32FPRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::STQDr32
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: SPU::STQXr32;
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} else if (RC == SPU::R16CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
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SPU::STQDr16
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: SPU::STQXr16;
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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addFrameReference(BuildMI(MBB, MI, TII.get(opc)).addReg(SrcReg), FrameIdx);
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}
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void SPURegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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cerr << "storeRegToAddr() invoked!\n";
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abort();
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if (Addr[0].isFrameIndex()) {
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/* do what storeRegToStackSlot does here */
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} else {
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unsigned Opc = 0;
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if (RC == SPU::GPRCRegisterClass) {
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/* Opc = PPC::STW; */
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} else if (RC == SPU::R16CRegisterClass) {
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/* Opc = PPC::STD; */
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} else if (RC == SPU::R32CRegisterClass) {
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/* Opc = PPC::STFD; */
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} else if (RC == SPU::R32FPRegisterClass) {
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/* Opc = PPC::STFD; */
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} else if (RC == SPU::R64FPRegisterClass) {
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/* Opc = PPC::STFS; */
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} else if (RC == SPU::VECREGRegisterClass) {
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/* Opc = PPC::STVX; */
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
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.addReg(SrcReg, false, false, true);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImmedValue());
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else
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MIB.addFrameIndex(MO.getFrameIndex());
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}
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NewMIs.push_back(MIB);
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}
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}
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void
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SPURegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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MachineOpCode opc;
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if (RC == SPU::GPRCRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr128
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: SPU::LQXr128;
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} else if (RC == SPU::R64CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr64
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: SPU::LQXr64;
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} else if (RC == SPU::R64FPRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr64
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: SPU::LQXr64;
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} else if (RC == SPU::R32CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr32
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: SPU::LQXr32;
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} else if (RC == SPU::R32FPRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr32
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: SPU::LQXr32;
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} else if (RC == SPU::R16CRegisterClass) {
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opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
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? SPU::LQDr16
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: SPU::LQXr16;
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} else {
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assert(0 && "Unknown regclass in loadRegFromStackSlot!");
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abort();
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}
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addFrameReference(BuildMI(MBB, MI, TII.get(opc)).addReg(DestReg), FrameIdx);
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}
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/*!
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\note We are really pessimistic here about what kind of a load we're doing.
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*/
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void SPURegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs)
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const {
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cerr << "loadRegToAddr() invoked!\n";
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abort();
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if (Addr[0].isFrameIndex()) {
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/* do what loadRegFromStackSlot does here... */
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} else {
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unsigned Opc = 0;
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if (RC == SPU::R16CRegisterClass) {
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/* Opc = PPC::LWZ; */
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} else if (RC == SPU::R32CRegisterClass) {
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/* Opc = PPC::LD; */
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} else if (RC == SPU::R32FPRegisterClass) {
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/* Opc = PPC::LFD; */
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} else if (RC == SPU::R64FPRegisterClass) {
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/* Opc = PPC::LFS; */
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} else if (RC == SPU::VECREGRegisterClass) {
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/* Opc = PPC::LVX; */
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} else if (RC == SPU::GPRCRegisterClass) {
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/* Opc = something else! */
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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}
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MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
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MachineOperand &MO = Addr[i];
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if (MO.isRegister())
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MIB.addReg(MO.getReg());
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else if (MO.isImmediate())
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MIB.addImm(MO.getImmedValue());
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else
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MIB.addFrameIndex(MO.getFrameIndex());
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}
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NewMIs.push_back(MIB);
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}
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}
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void SPURegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const
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{
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if (DestRC != SrcRC) {
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cerr << "SPURegisterInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
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abort();
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}
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/* if (DestRC == SPU::R8CRegisterClass) {
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BuildMI(MBB, MI, TII.get(SPU::ORBIr8), DestReg).addReg(SrcReg).addImm(0);
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} else */
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if (DestRC == SPU::R16CRegisterClass) {
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BuildMI(MBB, MI, TII.get(SPU::ORHIr16), DestReg).addReg(SrcReg).addImm(0);
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} else if (DestRC == SPU::R32CRegisterClass) {
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BuildMI(MBB, MI, TII.get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
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} else if (DestRC == SPU::R32FPRegisterClass) {
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BuildMI(MBB, MI, TII.get(SPU::ORIf32), DestReg).addReg(SrcReg).addImm(0);
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} else if (DestRC == SPU::R64CRegisterClass) {
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BuildMI(MBB, MI, TII.get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0);
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} else if (DestRC == SPU::R64FPRegisterClass) {
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BuildMI(MBB, MI, TII.get(SPU::ORIf64), DestReg).addReg(SrcReg).addImm(0);
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} else if (DestRC == SPU::GPRCRegisterClass) {
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BuildMI(MBB, MI, TII.get(SPU::ORgprc), DestReg).addReg(SrcReg)
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.addReg(SrcReg);
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} else if (DestRC == SPU::VECREGRegisterClass) {
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BuildMI(MBB, MI, TII.get(SPU::ORv4i32), DestReg).addReg(SrcReg)
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.addReg(SrcReg);
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} else {
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std::cerr << "Attempt to copy unknown/unsupported register class!\n";
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abort();
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}
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}
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void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const {
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MachineInstr *MI = Orig->clone();
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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// SPU's 128-bit registers used for argument passing:
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static const unsigned SPU_ArgRegs[] = {
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SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9,
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SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16,
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SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23,
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SPU::R24, SPU::R25, SPU::R26, SPU::R27, SPU::R28, SPU::R29, SPU::R30,
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SPU::R31, SPU::R32, SPU::R33, SPU::R34, SPU::R35, SPU::R36, SPU::R37,
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SPU::R38, SPU::R39, SPU::R40, SPU::R41, SPU::R42, SPU::R43, SPU::R44,
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SPU::R45, SPU::R46, SPU::R47, SPU::R48, SPU::R49, SPU::R50, SPU::R51,
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SPU::R52, SPU::R53, SPU::R54, SPU::R55, SPU::R56, SPU::R57, SPU::R58,
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SPU::R59, SPU::R60, SPU::R61, SPU::R62, SPU::R63, SPU::R64, SPU::R65,
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SPU::R66, SPU::R67, SPU::R68, SPU::R69, SPU::R70, SPU::R71, SPU::R72,
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SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79
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};
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const unsigned *
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SPURegisterInfo::getArgRegs()
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{
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return SPU_ArgRegs;
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}
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const unsigned
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SPURegisterInfo::getNumArgRegs()
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{
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return sizeof(SPU_ArgRegs) / sizeof(SPU_ArgRegs[0]);
|
|
}
|
|
|
|
const unsigned *
|
|
SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const
|
|
{
|
|
// Cell ABI calling convention
|
|
static const unsigned SPU_CalleeSaveRegs[] = {
|
|
SPU::R80, SPU::R81, SPU::R82, SPU::R83,
|
|
SPU::R84, SPU::R85, SPU::R86, SPU::R87,
|
|
SPU::R88, SPU::R89, SPU::R90, SPU::R91,
|
|
SPU::R92, SPU::R93, SPU::R94, SPU::R95,
|
|
SPU::R96, SPU::R97, SPU::R98, SPU::R99,
|
|
SPU::R100, SPU::R101, SPU::R102, SPU::R103,
|
|
SPU::R104, SPU::R105, SPU::R106, SPU::R107,
|
|
SPU::R108, SPU::R109, SPU::R110, SPU::R111,
|
|
SPU::R112, SPU::R113, SPU::R114, SPU::R115,
|
|
SPU::R116, SPU::R117, SPU::R118, SPU::R119,
|
|
SPU::R120, SPU::R121, SPU::R122, SPU::R123,
|
|
SPU::R124, SPU::R125, SPU::R126, SPU::R127,
|
|
SPU::R2, /* environment pointer */
|
|
SPU::R1, /* stack pointer */
|
|
SPU::R0, /* link register */
|
|
0 /* end */
|
|
};
|
|
|
|
return SPU_CalleeSaveRegs;
|
|
}
|
|
|
|
const TargetRegisterClass* const*
|
|
SPURegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const
|
|
{
|
|
// Cell ABI Calling Convention
|
|
static const TargetRegisterClass * const SPU_CalleeSaveRegClasses[] = {
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, &SPU::GPRCRegClass, &SPU::GPRCRegClass,
|
|
&SPU::GPRCRegClass, /* environment pointer */
|
|
&SPU::GPRCRegClass, /* stack pointer */
|
|
&SPU::GPRCRegClass, /* link register */
|
|
0 /* end */
|
|
};
|
|
|
|
return SPU_CalleeSaveRegClasses;
|
|
}
|
|
|
|
/*!
|
|
R0 (link register), R1 (stack pointer) and R2 (environment pointer -- this is
|
|
generally unused) are the Cell's reserved registers
|
|
*/
|
|
BitVector SPURegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|
BitVector Reserved(getNumRegs());
|
|
Reserved.set(SPU::R0); // LR
|
|
Reserved.set(SPU::R1); // SP
|
|
Reserved.set(SPU::R2); // environment pointer
|
|
return Reserved;
|
|
}
|
|
|
|
/// foldMemoryOperand - SPU, like PPC, can only fold spills into
|
|
/// copy instructions, turning them into load/store instructions.
|
|
MachineInstr *
|
|
SPURegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
|
|
int FrameIndex) const
|
|
{
|
|
#if SOMEDAY_SCOTT_LOOKS_AT_ME_AGAIN
|
|
unsigned Opc = MI->getOpcode();
|
|
MachineInstr *NewMI = 0;
|
|
|
|
if ((Opc == SPU::ORr32
|
|
|| Opc == SPU::ORv4i32)
|
|
&& MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned InReg = MI->getOperand(1).getReg();
|
|
if (FrameIndex < SPUFrameInfo::maxFrameOffset()) {
|
|
NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)).addReg(InReg),
|
|
FrameIndex);
|
|
}
|
|
} else { // move -> load
|
|
unsigned OutReg = MI->getOperand(0).getReg();
|
|
Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32;
|
|
NewMI = addFrameReference(BuildMI(TII.get(Opc), OutReg), FrameIndex);
|
|
}
|
|
}
|
|
|
|
if (NewMI)
|
|
NewMI->copyKillDeadInfo(MI);
|
|
|
|
return NewMI;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
/// General-purpose load/store fold to operand code
|
|
MachineInstr *
|
|
SPURegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum,
|
|
MachineInstr *LoadMI) const
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Stack Frame Processing methods
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// needsFP - Return true if the specified function should have a dedicated frame
|
|
// pointer register. This is true if the function has variable sized allocas or
|
|
// if frame pointer elimination is disabled.
|
|
//
|
|
static bool needsFP(const MachineFunction &MF) {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
return NoFramePointerElim || MFI->hasVarSizedObjects();
|
|
}
|
|
|
|
//--------------------------------------------------------------------------
|
|
// hasFP - Return true if the specified function actually has a dedicated frame
|
|
// pointer register. This is true if the function needs a frame pointer and has
|
|
// a non-zero stack size.
|
|
bool
|
|
SPURegisterInfo::hasFP(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
return MFI->getStackSize() && needsFP(MF);
|
|
}
|
|
|
|
//--------------------------------------------------------------------------
|
|
void
|
|
SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
|
|
MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I)
|
|
const
|
|
{
|
|
// Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
|
|
MBB.erase(I);
|
|
}
|
|
|
|
void
|
|
SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
|
RegScavenger *RS) const
|
|
{
|
|
assert(SPAdj == 0 && "Unexpected SP adjacency == 0");
|
|
|
|
unsigned i = 0;
|
|
MachineInstr &MI = *II;
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineFunction &MF = *MBB.getParent();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
while (!MI.getOperand(i).isFrameIndex()) {
|
|
++i;
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
}
|
|
|
|
MachineOperand &SPOp = MI.getOperand(i);
|
|
int FrameIndex = SPOp.getFrameIndex();
|
|
|
|
// Now add the frame object offset to the offset from r1.
|
|
int Offset = MFI->getObjectOffset(FrameIndex);
|
|
|
|
// Most instructions, except for generated FrameIndex additions using AIr32,
|
|
// have the immediate in operand 1. AIr32, in this case, has the immediate
|
|
// in operand 2.
|
|
unsigned OpNo = (MI.getOpcode() != SPU::AIr32 ? 1 : 2);
|
|
MachineOperand &MO = MI.getOperand(OpNo);
|
|
|
|
// Offset is biased by $lr's slot at the bottom.
|
|
Offset += MO.getImmedValue() + MFI->getStackSize()
|
|
+ SPUFrameInfo::minStackSize();
|
|
assert((Offset & 0xf) == 0
|
|
&& "16-byte alignment violated in SPURegisterInfo::eliminateFrameIndex");
|
|
|
|
// Replace the FrameIndex with base register with $sp (aka $r1)
|
|
SPOp.ChangeToRegister(SPU::R1, false);
|
|
if (Offset > SPUFrameInfo::maxFrameOffset()
|
|
|| Offset < SPUFrameInfo::minFrameOffset()) {
|
|
cerr << "Large stack adjustment ("
|
|
<< Offset
|
|
<< ") in SPURegisterInfo::eliminateFrameIndex.";
|
|
} else {
|
|
MO.ChangeToImmediate(Offset);
|
|
}
|
|
}
|
|
|
|
/// determineFrameLayout - Determine the size of the frame and maximum call
|
|
/// frame size.
|
|
void
|
|
SPURegisterInfo::determineFrameLayout(MachineFunction &MF) const
|
|
{
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
// Get the number of bytes to allocate from the FrameInfo
|
|
unsigned FrameSize = MFI->getStackSize();
|
|
|
|
// Get the alignments provided by the target, and the maximum alignment
|
|
// (if any) of the fixed frame objects.
|
|
unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
|
|
unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment());
|
|
assert(isPowerOf2_32(Align) && "Alignment is not power of 2");
|
|
unsigned AlignMask = Align - 1;
|
|
|
|
// Get the maximum call frame size of all the calls.
|
|
unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
|
|
|
|
// If we have dynamic alloca then maxCallFrameSize needs to be aligned so
|
|
// that allocations will be aligned.
|
|
if (MFI->hasVarSizedObjects())
|
|
maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
|
|
|
|
// Update maximum call frame size.
|
|
MFI->setMaxCallFrameSize(maxCallFrameSize);
|
|
|
|
// Include call frame size in total.
|
|
FrameSize += maxCallFrameSize;
|
|
|
|
// Make sure the frame is aligned.
|
|
FrameSize = (FrameSize + AlignMask) & ~AlignMask;
|
|
|
|
// Update frame info.
|
|
MFI->setStackSize(FrameSize);
|
|
}
|
|
|
|
void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
|
RegScavenger *RS)
|
|
const {
|
|
#if 0
|
|
// Save and clear the LR state.
|
|
SPUFunctionInfo *FI = MF.getInfo<SPUFunctionInfo>();
|
|
FI->setUsesLR(MF.isPhysRegUsed(LR));
|
|
#endif
|
|
// Mark LR and SP unused, since the prolog spills them to stack and
|
|
// we don't want anyone else to spill them for us.
|
|
//
|
|
// Also, unless R2 is really used someday, don't spill it automatically.
|
|
MF.setPhysRegUnused(SPU::R0);
|
|
MF.setPhysRegUnused(SPU::R1);
|
|
MF.setPhysRegUnused(SPU::R2);
|
|
}
|
|
|
|
void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
|
|
{
|
|
MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
|
|
MachineBasicBlock::iterator MBBI = MBB.begin();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
|
|
|
|
// Prepare for debug frame info.
|
|
bool hasDebugInfo = MMI && MMI->hasDebugInfo();
|
|
unsigned FrameLabelId = 0;
|
|
|
|
// Move MBBI back to the beginning of the function.
|
|
MBBI = MBB.begin();
|
|
|
|
// Work out frame sizes.
|
|
determineFrameLayout(MF);
|
|
int FrameSize = MFI->getStackSize();
|
|
|
|
assert((FrameSize & 0xf) == 0
|
|
&& "SPURegisterInfo::emitPrologue: FrameSize not aligned");
|
|
|
|
if (FrameSize > 0) {
|
|
FrameSize = -(FrameSize + SPUFrameInfo::minStackSize());
|
|
if (hasDebugInfo) {
|
|
// Mark effective beginning of when frame pointer becomes valid.
|
|
FrameLabelId = MMI->NextLabelID();
|
|
BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(FrameLabelId);
|
|
}
|
|
|
|
// Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
|
|
// for the ABI
|
|
BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
|
|
.addReg(SPU::R1);
|
|
if (isS10Constant(FrameSize)) {
|
|
// Spill $sp to adjusted $sp
|
|
BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
|
|
.addReg(SPU::R1);
|
|
// Adjust $sp by required amout
|
|
BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
|
|
.addImm(FrameSize);
|
|
} else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
|
|
// Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
|
|
// $r2 to adjust $sp:
|
|
BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
|
|
.addImm(-16)
|
|
.addReg(SPU::R1);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
|
|
.addImm(FrameSize);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::STQDr32), SPU::R1)
|
|
.addReg(SPU::R2)
|
|
.addReg(SPU::R1);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
|
|
.addReg(SPU::R1)
|
|
.addReg(SPU::R2);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2)
|
|
.addReg(SPU::R2)
|
|
.addImm(16);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
|
|
.addReg(SPU::R2)
|
|
.addReg(SPU::R1);
|
|
} else {
|
|
cerr << "Unhandled frame size: " << FrameSize << "\n";
|
|
abort();
|
|
}
|
|
|
|
if (hasDebugInfo) {
|
|
std::vector<MachineMove> &Moves = MMI->getFrameMoves();
|
|
|
|
// Show update of SP.
|
|
MachineLocation SPDst(MachineLocation::VirtualFP);
|
|
MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize);
|
|
Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
|
|
|
|
// Add callee saved registers to move list.
|
|
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
|
|
for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
|
|
int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
|
|
unsigned Reg = CSI[I].getReg();
|
|
if (Reg == SPU::R0) continue;
|
|
MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
|
|
MachineLocation CSSrc(Reg);
|
|
Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc));
|
|
}
|
|
|
|
// Mark effective beginning of when frame pointer is ready.
|
|
unsigned ReadyLabelId = MMI->NextLabelID();
|
|
BuildMI(MBB, MBBI, TII.get(ISD::LABEL)).addImm(ReadyLabelId);
|
|
|
|
MachineLocation FPDst(SPU::R1);
|
|
MachineLocation FPSrc(MachineLocation::VirtualFP);
|
|
Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
|
|
}
|
|
} else {
|
|
// This is a leaf function -- insert a branch hint iff there are
|
|
// sufficient number instructions in the basic block. Note that
|
|
// this is just a best guess based on the basic block's size.
|
|
if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) {
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
// Insert terminator label
|
|
unsigned BranchLabelId = MMI->NextLabelID();
|
|
BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
|
|
{
|
|
MachineBasicBlock::iterator MBBI = prior(MBB.end());
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
int FrameSize = MFI->getStackSize();
|
|
int LinkSlotOffset = SPUFrameInfo::stackSlotSize();
|
|
|
|
assert(MBBI->getOpcode() == SPU::RET &&
|
|
"Can only insert epilog into returning blocks");
|
|
assert((FrameSize & 0xf) == 0
|
|
&& "SPURegisterInfo::emitEpilogue: FrameSize not aligned");
|
|
if (FrameSize > 0) {
|
|
FrameSize = FrameSize + SPUFrameInfo::minStackSize();
|
|
if (isS10Constant(FrameSize + LinkSlotOffset)) {
|
|
// Reload $lr, adjust $sp by required amount
|
|
// Note: We do this to slightly improve dual issue -- not by much, but it
|
|
// is an opportunity for dual issue.
|
|
BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
|
|
.addImm(FrameSize + LinkSlotOffset)
|
|
.addReg(SPU::R1);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::AIr32), SPU::R1)
|
|
.addReg(SPU::R1)
|
|
.addImm(FrameSize);
|
|
} else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
|
|
// Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
|
|
// $r2 to adjust $sp:
|
|
BuildMI(MBB, MBBI, TII.get(SPU::STQDr128), SPU::R2)
|
|
.addImm(16)
|
|
.addReg(SPU::R1);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::ILr32), SPU::R2)
|
|
.addImm(FrameSize);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::Ar32), SPU::R1)
|
|
.addReg(SPU::R1)
|
|
.addReg(SPU::R2);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::LQDr128), SPU::R0)
|
|
.addImm(16)
|
|
.addReg(SPU::R2);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::SFIr32), SPU::R2).
|
|
addReg(SPU::R2)
|
|
.addImm(16);
|
|
BuildMI(MBB, MBBI, TII.get(SPU::LQXr128), SPU::R2)
|
|
.addReg(SPU::R2)
|
|
.addReg(SPU::R1);
|
|
} else {
|
|
cerr << "Unhandled frame size: " << FrameSize << "\n";
|
|
abort();
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned
|
|
SPURegisterInfo::getRARegister() const
|
|
{
|
|
return SPU::R0;
|
|
}
|
|
|
|
unsigned
|
|
SPURegisterInfo::getFrameRegister(MachineFunction &MF) const
|
|
{
|
|
return SPU::R1;
|
|
}
|
|
|
|
void
|
|
SPURegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const
|
|
{
|
|
// Initial state of the frame pointer is R1.
|
|
MachineLocation Dst(MachineLocation::VirtualFP);
|
|
MachineLocation Src(SPU::R1, 0);
|
|
Moves.push_back(MachineMove(0, Dst, Src));
|
|
}
|
|
|
|
|
|
int
|
|
SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
|
|
// FIXME: Most probably dwarf numbers differs for Linux and Darwin
|
|
return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
|
|
}
|
|
|
|
#include "SPUGenRegisterInfo.inc"
|