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28b77e968d
with a vector condition); such selects become VSELECT codegen nodes. This patch also removes VSETCC codegen nodes, unifying them with SETCC nodes (codegen was actually often using SETCC for vector SETCC already). This ensures that various DAG combiner optimizations kick in for vector comparisons. Passes dragonegg bootstrap with no testsuite regressions (nightly testsuite as well as "make check-all"). Patch mostly by Nadav Rotem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
84 lines
3.3 KiB
C++
84 lines
3.3 KiB
C++
//===- BlackfinISelLowering.h - Blackfin DAG Lowering Interface -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Blackfin uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef BLACKFIN_ISELLOWERING_H
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#define BLACKFIN_ISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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#include "Blackfin.h"
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namespace llvm {
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namespace BFISD {
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enum {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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CALL, // A call instruction.
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RET_FLAG, // Return with a flag operand.
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Wrapper // Address wrapper
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};
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}
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class BlackfinTargetLowering : public TargetLowering {
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public:
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BlackfinTargetLowering(TargetMachine &TM);
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virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i16; }
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virtual EVT getSetCCResultType(EVT VT) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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virtual void ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const;
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ConstraintType getConstraintType(const std::string &Constraint) const;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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const char *getTargetNodeName(unsigned Opcode) const;
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private:
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerADDE(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual SDValue
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const;
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};
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} // end namespace llvm
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#endif // BLACKFIN_ISELLOWERING_H
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