mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
191 lines
4.6 KiB
LLVM
191 lines
4.6 KiB
LLVM
; Test 32-bit rotates left.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check the low end of the RLLG range.
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define i64 @f1(i64 %a) {
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; CHECK-LABEL: f1:
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; CHECK: rllg %r2, %r2, 1
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; CHECK: br %r14
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%parta = shl i64 %a, 1
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%partb = lshr i64 %a, 63
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check the high end of the defined RLLG range.
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define i64 @f2(i64 %a) {
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; CHECK-LABEL: f2:
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; CHECK: rllg %r2, %r2, 63
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; CHECK: br %r14
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%parta = shl i64 %a, 63
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%partb = lshr i64 %a, 1
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; We don't generate shifts by out-of-range values.
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define i64 @f3(i64 %a) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: rllg
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; CHECK: br %r14
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%parta = shl i64 %a, 64
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%partb = lshr i64 %a, 0
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check variable shifts.
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define i64 @f4(i64 %a, i64 %amt) {
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; CHECK-LABEL: f4:
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; CHECK: rllg %r2, %r2, 0(%r3)
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; CHECK: br %r14
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%amtb = sub i64 64, %amt
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%parta = shl i64 %a, %amt
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%partb = lshr i64 %a, %amtb
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check shift amounts that have a constant term.
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define i64 @f5(i64 %a, i64 %amt) {
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; CHECK-LABEL: f5:
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; CHECK: rllg %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i64 %amt, 10
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%sub = sub i64 64, %add
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%parta = shl i64 %a, %add
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%partb = lshr i64 %a, %sub
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; ...and again with a sign-extended 32-bit shift amount.
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define i64 @f6(i64 %a, i32 %amt) {
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; CHECK-LABEL: f6:
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; CHECK: rllg %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 10
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%sub = sub i32 64, %add
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%addext = sext i32 %add to i64
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%subext = sext i32 %sub to i64
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%parta = shl i64 %a, %addext
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%partb = lshr i64 %a, %subext
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; ...and now with a zero-extended 32-bit shift amount.
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define i64 @f7(i64 %a, i32 %amt) {
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; CHECK-LABEL: f7:
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; CHECK: rllg %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 10
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%sub = sub i32 64, %add
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%addext = zext i32 %add to i64
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%subext = zext i32 %sub to i64
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%parta = shl i64 %a, %addext
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%partb = lshr i64 %a, %subext
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check shift amounts that have the largest in-range constant term. We could
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; mask the amount instead.
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define i64 @f8(i64 %a, i64 %amt) {
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; CHECK-LABEL: f8:
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; CHECK: rllg %r2, %r2, 524287(%r3)
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; CHECK: br %r14
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%add = add i64 %amt, 524287
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%sub = sub i64 64, %add
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%parta = shl i64 %a, %add
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%partb = lshr i64 %a, %sub
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check the next value up, which without masking must use a separate
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; addition.
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define i64 @f9(i64 %a, i64 %amt) {
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; CHECK-LABEL: f9:
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; CHECK: a{{g?}}fi %r3, 524288
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; CHECK: rllg %r2, %r2, 0(%r3)
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; CHECK: br %r14
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%add = add i64 %amt, 524288
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%sub = sub i64 64, %add
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%parta = shl i64 %a, %add
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%partb = lshr i64 %a, %sub
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check cases where 1 is subtracted from the shift amount.
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define i64 @f10(i64 %a, i64 %amt) {
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; CHECK-LABEL: f10:
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; CHECK: rllg %r2, %r2, -1(%r3)
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; CHECK: br %r14
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%suba = sub i64 %amt, 1
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%subb = sub i64 64, %suba
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%parta = shl i64 %a, %suba
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%partb = lshr i64 %a, %subb
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check the lowest value that can be subtracted from the shift amount.
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; Again, we could mask the shift amount instead.
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define i64 @f11(i64 %a, i64 %amt) {
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; CHECK-LABEL: f11:
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; CHECK: rllg %r2, %r2, -524288(%r3)
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; CHECK: br %r14
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%suba = sub i64 %amt, 524288
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%subb = sub i64 64, %suba
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%parta = shl i64 %a, %suba
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%partb = lshr i64 %a, %subb
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check the next value down, which without masking must use a separate
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; addition.
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define i64 @f12(i64 %a, i64 %amt) {
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; CHECK-LABEL: f12:
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; CHECK: a{{g?}}fi %r3, -524289
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; CHECK: rllg %r2, %r2, 0(%r3)
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; CHECK: br %r14
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%suba = sub i64 %amt, 524289
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%subb = sub i64 64, %suba
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%parta = shl i64 %a, %suba
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%partb = lshr i64 %a, %subb
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check that we don't try to generate "indexed" shifts.
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define i64 @f13(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: f13:
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; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
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; CHECK: rllg %r2, %r2, 0({{%r[34]}})
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; CHECK: br %r14
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%add = add i64 %b, %c
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%sub = sub i64 64, %add
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%parta = shl i64 %a, %add
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%partb = lshr i64 %a, %sub
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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; Check that the shift amount uses an address register. It cannot be in %r0.
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define i64 @f14(i64 %a, i64 *%ptr) {
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; CHECK-LABEL: f14:
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; CHECK: l %r1, 4(%r3)
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; CHECK: rllg %r2, %r2, 0(%r1)
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; CHECK: br %r14
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%amt = load i64 , i64 *%ptr
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%amtb = sub i64 64, %amt
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%parta = shl i64 %a, %amt
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%partb = lshr i64 %a, %amtb
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%or = or i64 %parta, %partb
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ret i64 %or
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}
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