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https://github.com/c64scene-ar/llvm-6502.git
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aa5c996eda
This the first of a series of patches to add CodeGen support exploiting the instructions of the z13 vector facility. This patch adds support for the native integer vector types (v16i8, v8i16, v4i32, v2i64). When the vector facility is present, we default to the new vector ABI. This is characterized by two major differences: - Vector types are passed/returned in vector registers (except for unnamed arguments of a variable-argument list function). - Vector types are at most 8-byte aligned. The reason for the choice of 8-byte vector alignment is that the hardware is able to efficiently load vectors at 8-byte alignment, and the ABI only guarantees 8-byte alignment of the stack pointer, so requiring any higher alignment for vectors would require dynamic stack re-alignment code. However, for compatibility with old code that may use vector types, when *not* using the vector facility, the old alignment rules (vector types are naturally aligned) remain in use. These alignment rules are not only implemented at the C language level (implemented in clang), but also at the LLVM IR level. This is done by selecting a different DataLayout string depending on whether the vector ABI is in effect or not. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236521 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.3 KiB
LLVM
86 lines
2.3 KiB
LLVM
; Test vector replicates that use VECTOR GENERATE MASK, v4i32 version.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a word-granularity replicate with the lowest value that cannot use
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; VREPIF.
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define <4 x i32> @f1() {
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; CHECK-LABEL: f1:
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; CHECK: vgmf %v24, 16, 16
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; CHECK: br %r14
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ret <4 x i32> <i32 32768, i32 32768, i32 32768, i32 32768>
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}
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; Test a word-granularity replicate that has the lower 17 bits set.
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define <4 x i32> @f2() {
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; CHECK-LABEL: f2:
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; CHECK: vgmf %v24, 15, 31
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; CHECK: br %r14
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ret <4 x i32> <i32 131071, i32 131071, i32 131071, i32 131071>
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}
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; Test a word-granularity replicate that has the upper 15 bits set.
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define <4 x i32> @f3() {
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; CHECK-LABEL: f3:
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; CHECK: vgmf %v24, 0, 14
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; CHECK: br %r14
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ret <4 x i32> <i32 -131072, i32 -131072, i32 -131072, i32 -131072>
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}
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; Test a word-granularity replicate that has middle bits set.
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define <4 x i32> @f4() {
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; CHECK-LABEL: f4:
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; CHECK: vgmf %v24, 12, 17
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; CHECK: br %r14
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ret <4 x i32> <i32 1032192, i32 1032192, i32 1032192, i32 1032192>
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}
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; Test a word-granularity replicate with a wrap-around mask.
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define <4 x i32> @f5() {
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; CHECK-LABEL: f5:
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; CHECK: vgmf %v24, 17, 15
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; CHECK: br %r14
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ret <4 x i32> <i32 -32769, i32 -32769, i32 -32769, i32 -32769>
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}
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; Test a doubleword-granularity replicate with the lowest value that cannot
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; use VREPIG.
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define <4 x i32> @f6() {
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; CHECK-LABEL: f6:
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; CHECK: vgmg %v24, 48, 48
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; CHECK: br %r14
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ret <4 x i32> <i32 0, i32 32768, i32 0, i32 32768>
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}
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; Test a doubleword-granularity replicate that has the lower 22 bits set.
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define <4 x i32> @f7() {
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; CHECK-LABEL: f7:
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; CHECK: vgmg %v24, 42, 63
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; CHECK: br %r14
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ret <4 x i32> <i32 0, i32 4194303, i32 0, i32 4194303>
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}
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; Test a doubleword-granularity replicate that has the upper 45 bits set.
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define <4 x i32> @f8() {
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; CHECK-LABEL: f8:
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; CHECK: vgmg %v24, 0, 44
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; CHECK: br %r14
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ret <4 x i32> <i32 -1, i32 -524288, i32 -1, i32 -524288>
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}
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; Test a doubleword-granularity replicate that has middle bits set.
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define <4 x i32> @f9() {
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; CHECK-LABEL: f9:
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; CHECK: vgmg %v24, 31, 42
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; CHECK: br %r14
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ret <4 x i32> <i32 1, i32 -2097152, i32 1, i32 -2097152>
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}
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; Test a doubleword-granularity replicate with a wrap-around mask.
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define <4 x i32> @f10() {
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; CHECK-LABEL: f10:
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; CHECK: vgmg %v24, 18, 0
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; CHECK: br %r14
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ret <4 x i32> <i32 -2147467265, i32 -1, i32 -2147467265, i32 -1>
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}
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