llvm-6502/test/CodeGen/SystemZ/vec-conv-02.ll
Ulrich Weigand cf0fa9b9dd [SystemZ] Add CodeGen support for scalar f64 ops in vector registers
The z13 vector facility includes some instructions that operate only on the
high f64 in a v2f64, effectively extending the FP register set from 16
to 32 registers.  It's still better to use the old instructions if the
operands happen to fit though, since the older instructions have a shorter
encoding.

Based on a patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236524 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:28:34 +00:00

34 lines
976 B
LLVM

; Test conversions between different-sized float elements.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
; Test cases where both elements of a v2f64 are converted to f32s.
define void @f1(<2 x double> %val, <2 x float> *%ptr) {
; CHECK-LABEL: f1:
; CHECK: vledb {{%v[0-9]+}}, %v24, 0, 0
; CHECK: br %r14
%res = fptrunc <2 x double> %val to <2 x float>
store <2 x float> %res, <2 x float> *%ptr
ret void
}
; Test conversion of an f64 in a vector register to an f32.
define float @f2(<2 x double> %vec) {
; CHECK-LABEL: f2:
; CHECK: wledb %f0, %v24
; CHECK: br %r14
%scalar = extractelement <2 x double> %vec, i32 0
%ret = fptrunc double %scalar to float
ret float %ret
}
; Test conversion of an f32 in a vector register to an f64.
define double @f3(<4 x float> %vec) {
; CHECK-LABEL: f3:
; CHECK: wldeb %f0, %v24
; CHECK: br %r14
%scalar = extractelement <4 x float> %vec, i32 0
%ret = fpext float %scalar to double
ret double %ret
}