llvm-6502/test/CodeGen
Akira Hatanaka 24e79e55da 1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
Change these to patterns.
2. Add another 16 instructions.

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161272 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 22:57:02 +00:00
..
ARM [arm-fast-isel] Add support for shl, lshr, and ashr. 2012-08-03 02:37:48 +00:00
CellSPU Implement r160312 as target indepedenet dag combine. 2012-07-17 08:31:11 +00:00
CPP test commit 2012-07-18 17:53:05 +00:00
Generic Fix a bug in the scalarization of BUILD_VECTOR. BUILD_VECTOR elements may be wider than the output element type. Make sure to trunc them if needed. 2012-07-15 20:39:08 +00:00
Hexagon
MBlaze
Mips 1. Redo mips16 instructions to avoid multiple opcodes for same instruction. 2012-08-03 22:57:02 +00:00
MSP430
NVPTX Add llvm.fabs intrinsic. 2012-05-28 21:48:37 +00:00
PowerPC Fix the remaining TCL-style quotes found in the testsuite. This is 2012-07-02 19:09:46 +00:00
SPARC test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines. 2012-07-03 04:29:20 +00:00
Thumb Fix the remaining TCL-style quotes found in the testsuite. This is 2012-07-02 19:09:46 +00:00
Thumb2 [arm-fast-isel] Add support for vararg function calls. 2012-07-19 09:49:00 +00:00
X86 Fix memcmp code-gen to honor -fno-builtin. 2012-08-03 21:26:18 +00:00
XCore Fix pattern for MKMSK instruction. 2012-06-13 17:59:12 +00:00