llvm-6502/test/MC/X86
Chandler Carruth 7cd7154421 [x86] Fix a pretty horrible bug and inconsistency in the x86 asm
parsing (and latent bug in the instruction definitions).

This is effectively a revert of r136287 which tried to address
a specific and narrow case of immediate operands failing to be accepted
by x86 instructions with a pretty heavy hammer: it introduced a new kind
of operand that behaved differently. All of that is removed with this
commit, but the test cases are both preserved and enhanced.

The core problem that r136287 and this commit are trying to handle is
that gas accepts both of the following instructions:

  insertps $192, %xmm0, %xmm1
  insertps $-64, %xmm0, %xmm1

These will encode to the same byte sequence, with the immediate
occupying an 8-bit entry. The first form was fixed by r136287 but that
broke the prior handling of the second form! =[ Ironically, we would
still emit the second form in some cases and then be unable to
re-assemble the output.

The reason why the first instruction failed to be handled is because
prior to r136287 the operands ere marked 'i32i8imm' which forces them to
be sign-extenable. Clearly, that won't work for 192 in a single byte.
However, making thim zero-extended or "unsigned" doesn't really address
the core issue either because it breaks negative immediates. The correct
fix is to make these operands 'i8imm' reflecting that they can be either
signed or unsigned but must be 8-bit immediates. This patch backs out
r136287 and then changes those places as well as some others to use
'i8imm' rather than one of the extended variants.

Naturally, this broke something else. The custom DAG nodes had to be
updated to have a much more accurate type constraint of an i8 node, and
a bunch of Pat immediates needed to be specified as i8 values.

The fallout didn't end there though. We also then ceased to be able to
match the instruction-specific intrinsics to the instructions so
modified. Digging, this is because they too used i32 rather than i8 in
their signature. So I've also switched those intrinsics to i8 arguments
in line with the instructions.

In order to make the intrinsic adjustments of course, I also had to add
auto upgrading for the intrinsics.

I suspect that the intrinsic argument types may have led everything down
this rabbit hole. Pretty happy with the result.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217310 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-06 10:00:01 +00:00
..
AlignedBundling
3DNow.s
2011-09-06-NoNewline.s
address-size.s
avx512-encodings.s [SKX] Added new versions of cmp instructions in avx512_icmp_cc multiclass, added VL multiclass. 2014-08-27 09:34:37 +00:00
cfi_def_cfa-crash.s
fde-reloc.s
fixup-cpu-mode.s
gnux32-dwarf-gen.s
index-operations.s
intel-syntax-2.s MC X86: Accept ".att_syntax prefix" and diagnose noprefix 2014-08-06 23:21:13 +00:00
intel-syntax-ambiguous.s X86 MC: Handle instructions like fxsave that match multiple operand sizes 2014-08-27 20:10:38 +00:00
intel-syntax-avx512.s
intel-syntax-bitwise-ops.s
intel-syntax-directional-label.s
intel-syntax-encoding.s
intel-syntax-error.s Add missing test for r215031 2014-08-11 18:34:54 +00:00
intel-syntax-hex.s
intel-syntax-invalid-basereg.s
intel-syntax-invalid-scale.s
intel-syntax-ptr-sized.s MC: Split the x86 asm matcher implementations by dialect 2014-08-26 20:32:34 +00:00
intel-syntax.s X86 MC: Handle instructions like fxsave that match multiple operand sizes 2014-08-27 20:10:38 +00:00
lit.local.cfg
macho-uleb.s Remove HasLEB128. 2014-08-15 14:01:07 +00:00
no-elf-compact-unwind.s Use compact unwind for the iOS simulator. 2014-06-20 22:40:55 +00:00
padlock.s
relax-insn.s
reloc-undef-global.s
ret.s
sgx-encoding.s Add support for the X86 secure guard extensions instructions in assembler (SGX). 2014-07-31 23:57:38 +00:00
shuffle-comments.s
stackmap-nops.ll [X86] Add comments to clarify some non-obvious lines in the stackmap-nops.ll 2014-07-25 04:50:08 +00:00
variant-diagnostics.s
x86_64-avx-clmul-encoding.s
x86_64-avx-encoding.s
x86_64-bmi-encoding.s
x86_64-encoding.s
x86_64-fma3-encoding.s
x86_64-fma4-encoding.s
x86_64-hle-encoding.s
x86_64-imm-widths.s
x86_64-rand-encoding.s
x86_64-rtm-encoding.s
x86_64-signed-reloc.s
x86_64-sse4a.s
x86_64-tbm-encoding.s
x86_64-xop-encoding.s
x86_directives.s
x86_errors.s X86 MC: Reject invalid segment registers before a memory operand colon 2014-07-31 23:03:22 +00:00
x86_long_nop.s [X86] Limit maximum nop length on Silvermont 2014-07-04 07:14:56 +00:00
x86_nop.s [X86] Limit maximum nop length on Silvermont 2014-07-04 07:14:56 +00:00
x86_operands.s X86 MC: Don't crash on empty memory operand parens 2014-07-31 23:26:35 +00:00
x86-16.s
x86-32-avx.s
x86-32-coverage.s [x86] Fix a pretty horrible bug and inconsistency in the x86 asm 2014-09-06 10:00:01 +00:00
x86-32-fma3.s
x86-32-ms-inline-asm.s Revert r212375 because of test failures 2014-07-05 19:46:10 +00:00
x86-32.s
x86-64-avx512bw_vl.s [SKX] Added new versions of cmp instructions in avx512_icmp_cc multiclass, added VL multiclass. 2014-08-27 09:34:37 +00:00
x86-64-avx512bw.s [SKX] Added new versions of cmp instructions in avx512_icmp_cc multiclass, added VL multiclass. 2014-08-27 09:34:37 +00:00
x86-64-avx512dq.s [SKX] Enabling mask logic instructions: encoding, lowering 2014-07-28 13:46:45 +00:00
x86-64-avx512f_vl.s [SKX] Added new versions of cmp instructions in avx512_icmp_cc multiclass, added VL multiclass. 2014-08-27 09:34:37 +00:00
x86-64.s
x86-itanium.ll MC: fix MCAsmInfo usage for windows-itanium 2014-07-17 16:27:40 +00:00
x86-target-directives.s
x86-windows-itanium-libcalls.ll X86: correct library call setup for Windows itanium 2014-07-24 17:46:36 +00:00