Chris Lattner 24faf611a3 fix the buildvector->insertp[sd] logic to not always create a redundant ... insertp[sd] $0, which is a noop. Before: _f32: ## @f32 pshufd $1, %xmm1, %xmm2 pshufd $1, %xmm0, %xmm3 addss %xmm2, %xmm3 addss %xmm1, %xmm0 ## kill: XMM0<def> XMM0<kill> XMM0<def> insertps $0, %xmm0, %xmm0 insertps $16, %xmm3, %xmm0 ret after: _f32: ## @f32 movdqa %xmm0, %xmm2 addss %xmm1, %xmm2 pshufd $1, %xmm1, %xmm1 pshufd $1, %xmm0, %xmm3 addss %xmm1, %xmm3 movdqa %xmm2, %xmm0 insertps $16, %xmm3, %xmm0 ret The extra movs are due to a random (poor) scheduling decision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112379 91177308-0d34-0410-b5e6-96231b3b80d8		2010-08-28 17:59:08 +00:00
..
Alpha
ARM	Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like	2010-08-27 23:18:17 +00:00
Blackfin
CBackend
CellSPU	Fix SPU BE to use all the available return registers.	2010-08-24 11:50:48 +00:00
CPP
Generic
MBlaze
Mips
MSP430
PIC16
PowerPC	PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.	2010-08-02 00:18:19 +00:00
SPARC
SystemZ
Thumb	Enable pre-RA virtual frame base register allocation. rdar://8277890	2010-08-26 00:58:06 +00:00
Thumb2	Add alignment arguments to all the NEON load/store intrinsics.	2010-08-27 17:13:24 +00:00
X86	fix the buildvector->insertp[sd] logic to not always create a redundant	2010-08-28 17:59:08 +00:00
XCore