llvm-6502/test/CodeGen
Juergen Ributzka e431884ed7 [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics.
This adds support for the cvttss2si/cvttsd2si intrinsics. Preceding
insertelement instructions are folded into the conversion instruction (if
possible).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210870 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-13 02:21:58 +00:00
..
AArch64 [AArch64] Basic Sched Model for Cortex-A57. 2014-06-11 21:06:56 +00:00
ARM CodeGen: enable mov.w/mov.t pairs with minsize for WoA 2014-06-12 20:06:33 +00:00
CPP
Generic
Hexagon
Inputs
Mips [mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 2014-06-12 15:00:17 +00:00
MSP430
NVPTX
PowerPC
R600 R600: Mostly remove remaining AMDIL intrinsics. 2014-06-12 21:15:44 +00:00
SPARC
SystemZ
Thumb Disable the load/store optimization pass for Thumb-1. 2014-06-12 15:18:33 +00:00
Thumb2
X86 [FastISel][X86] Add support for cvttss2si/cvttsd2si intrinsics. 2014-06-13 02:21:58 +00:00
XCore