mirror of
https://github.com/c64scene-ar/llvm-6502.git
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2a9d1ca9c2
The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
541 lines
22 KiB
TableGen
541 lines
22 KiB
TableGen
//===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 Register file, defining the registers themselves,
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// aliases between the registers, and the register classes built out of the
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// registers.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Register definitions...
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//
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let Namespace = "X86" in {
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// Subregister indices.
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def sub_8bit : SubRegIndex;
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def sub_8bit_hi : SubRegIndex;
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def sub_16bit : SubRegIndex;
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def sub_32bit : SubRegIndex;
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def sub_ss : SubRegIndex;
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def sub_sd : SubRegIndex;
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def sub_xmm : SubRegIndex;
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// In the register alias definitions below, we define which registers alias
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// which others. We only specify which registers the small registers alias,
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// because the register file generator is smart enough to figure out that
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// AL aliases AX if we tell it that AX aliased AL (for example).
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// Dwarf numbering is different for 32-bit and 64-bit, and there are
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// variations by target as well. Currently the first entry is for X86-64,
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// second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
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// and debug information on X86-32/Darwin)
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// 8-bit registers
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// Low registers
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def AL : Register<"al">;
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def DL : Register<"dl">;
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def CL : Register<"cl">;
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def BL : Register<"bl">;
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// X86-64 only, requires REX.
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let CostPerUse = 1 in {
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def SIL : Register<"sil">;
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def DIL : Register<"dil">;
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def BPL : Register<"bpl">;
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def SPL : Register<"spl">;
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def R8B : Register<"r8b">;
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def R9B : Register<"r9b">;
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def R10B : Register<"r10b">;
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def R11B : Register<"r11b">;
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def R12B : Register<"r12b">;
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def R13B : Register<"r13b">;
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def R14B : Register<"r14b">;
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def R15B : Register<"r15b">;
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}
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// High registers. On x86-64, these cannot be used in any instruction
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// with a REX prefix.
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def AH : Register<"ah">;
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def DH : Register<"dh">;
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def CH : Register<"ch">;
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def BH : Register<"bh">;
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// 16-bit registers
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let SubRegIndices = [sub_8bit, sub_8bit_hi] in {
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def AX : RegisterWithSubRegs<"ax", [AL,AH]>;
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def DX : RegisterWithSubRegs<"dx", [DL,DH]>;
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def CX : RegisterWithSubRegs<"cx", [CL,CH]>;
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def BX : RegisterWithSubRegs<"bx", [BL,BH]>;
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}
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let SubRegIndices = [sub_8bit] in {
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def SI : RegisterWithSubRegs<"si", [SIL]>;
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def DI : RegisterWithSubRegs<"di", [DIL]>;
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def BP : RegisterWithSubRegs<"bp", [BPL]>;
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def SP : RegisterWithSubRegs<"sp", [SPL]>;
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}
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def IP : Register<"ip">;
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// X86-64 only, requires REX.
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let SubRegIndices = [sub_8bit], CostPerUse = 1 in {
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def R8W : RegisterWithSubRegs<"r8w", [R8B]>;
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def R9W : RegisterWithSubRegs<"r9w", [R9B]>;
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def R10W : RegisterWithSubRegs<"r10w", [R10B]>;
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def R11W : RegisterWithSubRegs<"r11w", [R11B]>;
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def R12W : RegisterWithSubRegs<"r12w", [R12B]>;
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def R13W : RegisterWithSubRegs<"r13w", [R13B]>;
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def R14W : RegisterWithSubRegs<"r14w", [R14B]>;
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def R15W : RegisterWithSubRegs<"r15w", [R15B]>;
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}
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// 32-bit registers
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let SubRegIndices = [sub_16bit] in {
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def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[-2, 0, 0]>;
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def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[-2, 2, 2]>;
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def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[-2, 1, 1]>;
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def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[-2, 3, 3]>;
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def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[-2, 6, 6]>;
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def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[-2, 7, 7]>;
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def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[-2, 4, 5]>;
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def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[-2, 5, 4]>;
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def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[-2, 8, 8]>;
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// X86-64 only, requires REX
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let CostPerUse = 1 in {
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def R8D : RegisterWithSubRegs<"r8d", [R8W]>;
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def R9D : RegisterWithSubRegs<"r9d", [R9W]>;
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def R10D : RegisterWithSubRegs<"r10d", [R10W]>;
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def R11D : RegisterWithSubRegs<"r11d", [R11W]>;
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def R12D : RegisterWithSubRegs<"r12d", [R12W]>;
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def R13D : RegisterWithSubRegs<"r13d", [R13W]>;
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def R14D : RegisterWithSubRegs<"r14d", [R14W]>;
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def R15D : RegisterWithSubRegs<"r15d", [R15W]>;
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}}
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// 64-bit registers, X86-64 only
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let SubRegIndices = [sub_32bit] in {
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def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>;
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def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>;
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def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>;
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def RBX : RegisterWithSubRegs<"rbx", [EBX]>, DwarfRegNum<[3, -2, -2]>;
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def RSI : RegisterWithSubRegs<"rsi", [ESI]>, DwarfRegNum<[4, -2, -2]>;
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def RDI : RegisterWithSubRegs<"rdi", [EDI]>, DwarfRegNum<[5, -2, -2]>;
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def RBP : RegisterWithSubRegs<"rbp", [EBP]>, DwarfRegNum<[6, -2, -2]>;
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def RSP : RegisterWithSubRegs<"rsp", [ESP]>, DwarfRegNum<[7, -2, -2]>;
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// These also require REX.
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let CostPerUse = 1 in {
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def R8 : RegisterWithSubRegs<"r8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
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def R9 : RegisterWithSubRegs<"r9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
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def R10 : RegisterWithSubRegs<"r10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
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def R11 : RegisterWithSubRegs<"r11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
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def R12 : RegisterWithSubRegs<"r12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
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def R13 : RegisterWithSubRegs<"r13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
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def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
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def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
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def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>;
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}}
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// MMX Registers. These are actually aliased to ST0 .. ST7
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def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>;
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def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
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def MM2 : Register<"mm2">, DwarfRegNum<[43, 31, 31]>;
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def MM3 : Register<"mm3">, DwarfRegNum<[44, 32, 32]>;
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def MM4 : Register<"mm4">, DwarfRegNum<[45, 33, 33]>;
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def MM5 : Register<"mm5">, DwarfRegNum<[46, 34, 34]>;
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def MM6 : Register<"mm6">, DwarfRegNum<[47, 35, 35]>;
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def MM7 : Register<"mm7">, DwarfRegNum<[48, 36, 36]>;
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// Pseudo Floating Point registers
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def FP0 : Register<"fp0">;
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def FP1 : Register<"fp1">;
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def FP2 : Register<"fp2">;
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def FP3 : Register<"fp3">;
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def FP4 : Register<"fp4">;
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def FP5 : Register<"fp5">;
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def FP6 : Register<"fp6">;
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// XMM Registers, used by the various SSE instruction set extensions.
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// The sub_ss and sub_sd subregs are the same registers with another regclass.
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let CompositeIndices = [(sub_ss), (sub_sd)] in {
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def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>;
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def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>;
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def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>;
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def XMM3: Register<"xmm3">, DwarfRegNum<[20, 24, 24]>;
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def XMM4: Register<"xmm4">, DwarfRegNum<[21, 25, 25]>;
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def XMM5: Register<"xmm5">, DwarfRegNum<[22, 26, 26]>;
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def XMM6: Register<"xmm6">, DwarfRegNum<[23, 27, 27]>;
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def XMM7: Register<"xmm7">, DwarfRegNum<[24, 28, 28]>;
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// X86-64 only
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let CostPerUse = 1 in {
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def XMM8: Register<"xmm8">, DwarfRegNum<[25, -2, -2]>;
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def XMM9: Register<"xmm9">, DwarfRegNum<[26, -2, -2]>;
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def XMM10: Register<"xmm10">, DwarfRegNum<[27, -2, -2]>;
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def XMM11: Register<"xmm11">, DwarfRegNum<[28, -2, -2]>;
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def XMM12: Register<"xmm12">, DwarfRegNum<[29, -2, -2]>;
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def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>;
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def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>;
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def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>;
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}}
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// YMM Registers, used by AVX instructions
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let SubRegIndices = [sub_xmm] in {
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def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegAlias<XMM0>;
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def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegAlias<XMM1>;
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def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegAlias<XMM2>;
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def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegAlias<XMM3>;
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def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegAlias<XMM4>;
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def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegAlias<XMM5>;
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def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegAlias<XMM6>;
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def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegAlias<XMM7>;
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def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegAlias<XMM8>;
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def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegAlias<XMM9>;
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def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegAlias<XMM10>;
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def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegAlias<XMM11>;
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def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegAlias<XMM12>;
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def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegAlias<XMM13>;
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def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegAlias<XMM14>;
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def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias<XMM15>;
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}
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// Floating point stack registers
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def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
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def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
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def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
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def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
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def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
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def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
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def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
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def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
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// Status flags register
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def EFLAGS : Register<"flags">;
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// Segment registers
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def CS : Register<"cs">;
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def DS : Register<"ds">;
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def SS : Register<"ss">;
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def ES : Register<"es">;
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def FS : Register<"fs">;
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def GS : Register<"gs">;
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// Debug registers
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def DR0 : Register<"dr0">;
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def DR1 : Register<"dr1">;
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def DR2 : Register<"dr2">;
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def DR3 : Register<"dr3">;
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def DR4 : Register<"dr4">;
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def DR5 : Register<"dr5">;
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def DR6 : Register<"dr6">;
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def DR7 : Register<"dr7">;
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// Control registers
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def CR0 : Register<"cr0">;
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def CR1 : Register<"cr1">;
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def CR2 : Register<"cr2">;
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def CR3 : Register<"cr3">;
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def CR4 : Register<"cr4">;
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def CR5 : Register<"cr5">;
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def CR6 : Register<"cr6">;
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def CR7 : Register<"cr7">;
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def CR8 : Register<"cr8">;
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def CR9 : Register<"cr9">;
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def CR10 : Register<"cr10">;
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def CR11 : Register<"cr11">;
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def CR12 : Register<"cr12">;
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def CR13 : Register<"cr13">;
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def CR14 : Register<"cr14">;
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def CR15 : Register<"cr15">;
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// Pseudo index registers
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def EIZ : Register<"eiz">;
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def RIZ : Register<"riz">;
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}
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//===----------------------------------------------------------------------===//
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// Register Class Definitions... now that we have all of the pieces, define the
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// top-level register classes. The order specified in the register list is
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// implicitly defined to be the register allocation order.
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//
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// List call-clobbered registers before callee-save registers. RBX, RBP, (and
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// R12, R13, R14, and R15 for X86-64) are callee-save registers.
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// In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
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// R8B, ... R15B.
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// Allocate R12 and R13 last, as these require an extra byte when
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// encoded in x86_64 instructions.
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// FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
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// 64-bit mode. The main complication is that they cannot be encoded in an
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// instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
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// require a REX prefix. For example, "addb %ah, %dil" and "movzbl %ah, %r8d"
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// cannot be encoded.
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def GR8 : RegisterClass<"X86", [i8], 8,
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[AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
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R8B, R9B, R10B, R11B, R14B, R15B, R12B, R13B]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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static const unsigned X86_GR8_AO_64[] = {
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X86::AL, X86::CL, X86::DL, X86::SIL, X86::DIL,
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X86::R8B, X86::R9B, X86::R10B, X86::R11B,
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X86::BL, X86::R14B, X86::R15B, X86::R12B, X86::R13B, X86::BPL
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};
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GR8Class::iterator
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GR8Class::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit())
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return X86_GR8_AO_64;
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else
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return begin();
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}
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GR8Class::iterator
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GR8Class::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const TargetFrameLowering *TFI = TM.getFrameLowering();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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const X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
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// Does the function dedicate RBP / EBP to being a frame ptr?
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if (!Subtarget.is64Bit())
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// In 32-mode, none of the 8-bit registers aliases EBP or ESP.
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return begin() + 8;
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else if (TFI->hasFP(MF) || MFI->getReserveFP())
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// If so, don't allocate SPL or BPL.
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return array_endof(X86_GR8_AO_64) - 1;
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else
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// If not, just don't allocate SPL.
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return array_endof(X86_GR8_AO_64);
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}
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}];
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}
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def GR16 : RegisterClass<"X86", [i16], 16,
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[AX, CX, DX, SI, DI, BX, BP, SP,
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R8W, R9W, R10W, R11W, R14W, R15W, R12W, R13W]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)];
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}
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def GR32 : RegisterClass<"X86", [i32], 32,
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[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP,
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R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
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}
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// GR64 - 64-bit GPRs. This oddly includes RIP, which isn't accurate, since
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// RIP isn't really a register and it can't be used anywhere except in an
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// address, but it doesn't cause trouble.
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def GR64 : RegisterClass<"X86", [i64], 64,
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[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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RBX, R14, R15, R12, R13, RBP, RSP, RIP]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
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(GR16 sub_16bit),
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(GR32 sub_32bit)];
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}
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// Segment registers for use by MOV instructions (and others) that have a
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// segment register as one operand. Always contain a 16-bit segment
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// descriptor.
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def SEGMENT_REG : RegisterClass<"X86", [i16], 16, [CS, DS, SS, ES, FS, GS]>;
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// Debug registers.
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def DEBUG_REG : RegisterClass<"X86", [i32], 32,
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[DR0, DR1, DR2, DR3, DR4, DR5, DR6, DR7]>;
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// Control registers.
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def CONTROL_REG : RegisterClass<"X86", [i64], 64,
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[CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7, CR8,
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CR9, CR10, CR11, CR12, CR13, CR14, CR15]>;
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// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
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// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
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// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
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// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
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// and GR64_ABCD are classes for registers that support 8-bit h-register
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// operations.
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def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]>;
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def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]>;
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def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
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let SubRegClasses = [(GR8_ABCD_L sub_8bit), (GR8_ABCD_H sub_8bit_hi)];
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}
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def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
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let SubRegClasses = [(GR8_ABCD_L sub_8bit),
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(GR8_ABCD_H sub_8bit_hi),
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(GR16_ABCD sub_16bit)];
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}
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def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
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let SubRegClasses = [(GR8_ABCD_L sub_8bit),
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(GR8_ABCD_H sub_8bit_hi),
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(GR16_ABCD sub_16bit),
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(GR32_ABCD sub_32bit)];
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}
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def GR32_TC : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
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}
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def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI,
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R8, R9, R11, RIP]> {
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let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
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(GR16 sub_16bit),
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(GR32_TC sub_32bit)];
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}
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def GR64_TCW64 : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX,
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R8, R9, R11]>;
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// GR8_NOREX - GR8 registers which do not require a REX prefix.
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def GR8_NOREX : RegisterClass<"X86", [i8], 8,
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[AL, CL, DL, AH, CH, DH, BL, BH]> {
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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// In 64-bit mode, it's not safe to blindly allocate H registers.
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static const unsigned X86_GR8_NOREX_AO_64[] = {
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X86::AL, X86::CL, X86::DL, X86::BL
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};
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GR8_NOREXClass::iterator
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GR8_NOREXClass::allocation_order_begin(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit())
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return X86_GR8_NOREX_AO_64;
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else
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return begin();
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}
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GR8_NOREXClass::iterator
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GR8_NOREXClass::allocation_order_end(const MachineFunction &MF) const {
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const TargetMachine &TM = MF.getTarget();
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const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
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if (Subtarget.is64Bit())
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return array_endof(X86_GR8_NOREX_AO_64);
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else
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return end();
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|
}
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|
}];
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}
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// GR16_NOREX - GR16 registers which do not require a REX prefix.
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def GR16_NOREX : RegisterClass<"X86", [i16], 16,
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[AX, CX, DX, SI, DI, BX, BP, SP]> {
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let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi)];
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}
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// GR32_NOREX - GR32 registers which do not require a REX prefix.
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def GR32_NOREX : RegisterClass<"X86", [i32], 32,
|
|
[EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
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let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
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|
(GR16_NOREX sub_16bit)];
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}
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// GR64_NOREX - GR64 registers which do not require a REX prefix.
|
|
def GR64_NOREX : RegisterClass<"X86", [i64], 64,
|
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[RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP]> {
|
|
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
|
|
(GR16_NOREX sub_16bit),
|
|
(GR32_NOREX sub_32bit)];
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}
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|
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// GR32_NOSP - GR32 registers except ESP.
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def GR32_NOSP : RegisterClass<"X86", [i32], 32,
|
|
[EAX, ECX, EDX, ESI, EDI, EBX, EBP,
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R8D, R9D, R10D, R11D, R14D, R15D, R12D, R13D]> {
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|
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
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}
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|
|
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// GR64_NOSP - GR64 registers except RSP (and RIP).
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|
def GR64_NOSP : RegisterClass<"X86", [i64], 64,
|
|
[RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
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|
RBX, R14, R15, R12, R13, RBP]> {
|
|
let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
|
|
(GR16 sub_16bit),
|
|
(GR32_NOSP sub_32bit)];
|
|
}
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|
|
|
// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except
|
|
// ESP.
|
|
def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32,
|
|
[EAX, ECX, EDX, ESI, EDI, EBX, EBP]> {
|
|
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
|
|
(GR16_NOREX sub_16bit)];
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|
}
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|
|
|
// GR64_NOREX_NOSP - GR64_NOREX registers except RSP.
|
|
def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64,
|
|
[RAX, RCX, RDX, RSI, RDI, RBX, RBP]> {
|
|
let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
|
|
(GR16_NOREX sub_16bit),
|
|
(GR32_NOREX_NOSP sub_32bit)];
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|
}
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|
|
|
// A class to support the 'A' assembler constraint: EAX then EDX.
|
|
def GR32_AD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
|
|
let SubRegClasses = [(GR8_ABCD_L sub_8bit),
|
|
(GR8_ABCD_H sub_8bit_hi),
|
|
(GR16_ABCD sub_16bit)];
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|
}
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|
|
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// Scalar SSE2 floating point registers.
|
|
def FR32 : RegisterClass<"X86", [f32], 32,
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
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|
XMM8, XMM9, XMM10, XMM11,
|
|
XMM12, XMM13, XMM14, XMM15]>;
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|
|
|
def FR64 : RegisterClass<"X86", [f64], 64,
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
XMM8, XMM9, XMM10, XMM11,
|
|
XMM12, XMM13, XMM14, XMM15]>;
|
|
|
|
|
|
// FIXME: This sets up the floating point register files as though they are f64
|
|
// values, though they really are f80 values. This will cause us to spill
|
|
// values as 64-bit quantities instead of 80-bit quantities, which is much much
|
|
// faster on common hardware. In reality, this should be controlled by a
|
|
// command line option or something.
|
|
|
|
def RFP32 : RegisterClass<"X86",[f32], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
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|
def RFP64 : RegisterClass<"X86",[f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
|
|
def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
|
|
|
|
// Floating point stack registers (these are not allocatable by the
|
|
// register allocator - the floating point stackifier is responsible
|
|
// for transforming FPn allocations to STn registers)
|
|
def RST : RegisterClass<"X86", [f80, f64, f32], 32,
|
|
[ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
|
|
let isAllocatable = 0;
|
|
}
|
|
|
|
// Generic vector registers: VR64 and VR128.
|
|
def VR64: RegisterClass<"X86", [x86mmx], 64,
|
|
[MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
|
|
def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
|
|
[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
|
|
XMM8, XMM9, XMM10, XMM11,
|
|
XMM12, XMM13, XMM14, XMM15]> {
|
|
let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd)];
|
|
}
|
|
|
|
def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256,
|
|
[YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
|
|
YMM8, YMM9, YMM10, YMM11,
|
|
YMM12, YMM13, YMM14, YMM15]> {
|
|
let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
|
|
}
|
|
|
|
// Status flags registers.
|
|
def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> {
|
|
let CopyCost = -1; // Don't allow copying of status registers.
|
|
let isAllocatable = 0;
|
|
}
|