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https://github.com/c64scene-ar/llvm-6502.git
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42d60274ea
- Added ability to emit cross class register copies to the BBRU scheduler. - More aggressive backtracking. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42375 91177308-0d34-0410-b5e6-96231b3b80d8
97 lines
3.6 KiB
C++
97 lines
3.6 KiB
C++
//===- MRegisterInfo.cpp - Target Register Information Implementation -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MRegisterInfo interface.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/ADT/BitVector.h"
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using namespace llvm;
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MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
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regclass_iterator RCB, regclass_iterator RCE,
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int CFSO, int CFDO)
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: Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
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assert(NumRegs < FirstVirtualRegister &&
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"Target has too many physical registers!");
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CallFrameSetupOpcode = CFSO;
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CallFrameDestroyOpcode = CFDO;
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}
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MRegisterInfo::~MRegisterInfo() {}
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/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
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/// register.
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const TargetRegisterClass *
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MRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT,
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unsigned reg) const {
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assert(isPhysicalRegister(reg) && "reg must be a physical register");
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// Pick the register class of the right type that contains this physreg.
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for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I)
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if ((*I)->hasType(VT) && (*I)->contains(reg))
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return *I;
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assert(false && "Couldn't find the register class");
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return 0;
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}
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/// getAllocatableSetForRC - Toggle the bits that represent allocatable
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/// registers for the specific register class.
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static void getAllocatableSetForRC(MachineFunction &MF,
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const TargetRegisterClass *RC, BitVector &R){
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for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
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E = RC->allocation_order_end(MF); I != E; ++I)
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R.set(*I);
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}
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BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF,
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const TargetRegisterClass *RC) const {
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BitVector Allocatable(NumRegs);
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if (RC) {
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getAllocatableSetForRC(MF, RC, Allocatable);
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return Allocatable;
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}
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for (MRegisterInfo::regclass_iterator I = regclass_begin(),
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E = regclass_end(); I != E; ++I)
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getAllocatableSetForRC(MF, *I, Allocatable);
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return Allocatable;
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}
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/// getLocation - This method should return the actual location of a frame
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/// variable given the frame index. The location is returned in ML.
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/// Subclasses should override this method for special handling of frame
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/// variables and then call MRegisterInfo::getLocation for the default action.
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void MRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
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MachineLocation &ML) const {
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const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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ML.set(getFrameRegister(MF),
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MFI->getObjectOffset(Index) +
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MFI->getStackSize() -
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TFI.getOffsetOfLocalArea() +
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MFI->getOffsetAdjustment());
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}
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/// getInitialFrameState - Returns a list of machine moves that are assumed
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/// on entry to a function.
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void
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MRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
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// Default is to do nothing.
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}
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