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https://github.com/c64scene-ar/llvm-6502.git
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5bafff36c7
This is still a work in progress but most of the NEON instruction set is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
62 lines
1.7 KiB
LLVM
62 lines
1.7 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vceq\\.i8} %t | count 2
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; RUN: grep {vceq\\.i16} %t | count 2
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; RUN: grep {vceq\\.i32} %t | count 2
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; RUN: grep {vceq\\.f32} %t | count 2
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define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = vicmp eq <8 x i8> %tmp1, %tmp2
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = vicmp eq <4 x i16> %tmp1, %tmp2
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = vicmp eq <2 x i32> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = load <2 x float>* %B
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%tmp3 = vfcmp oeq <2 x float> %tmp1, %tmp2
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = vicmp eq <16 x i8> %tmp1, %tmp2
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = vicmp eq <8 x i16> %tmp1, %tmp2
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = vicmp eq <4 x i32> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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%tmp1 = load <4 x float>* %A
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%tmp2 = load <4 x float>* %B
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%tmp3 = vfcmp oeq <4 x float> %tmp1, %tmp2
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ret <4 x i32> %tmp3
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}
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