mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-30 05:29:47 +00:00
c0b0c677a1
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
419 lines
15 KiB
C++
419 lines
15 KiB
C++
//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This is the parent TargetLowering class for hardware code gen
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/// targets.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUISelLowering.h"
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#include "AMDILIntrinsicInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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using namespace llvm;
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AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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TargetLowering(TM, new TargetLoweringObjectFileELF()) {
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// Initialize target lowering borrowed from AMDIL
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InitAMDILLowering();
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// We need to custom lower some of the intrinsics
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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// Library functions. These default to Expand, but we have instructions
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// for them.
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setOperationAction(ISD::FCEIL, MVT::f32, Legal);
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setOperationAction(ISD::FEXP2, MVT::f32, Legal);
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setOperationAction(ISD::FPOW, MVT::f32, Legal);
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setOperationAction(ISD::FLOG2, MVT::f32, Legal);
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setOperationAction(ISD::FABS, MVT::f32, Legal);
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setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
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setOperationAction(ISD::FRINT, MVT::f32, Legal);
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// Lower floating point store/load to integer store/load to reduce the number
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// of patterns in tablegen.
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setOperationAction(ISD::STORE, MVT::f32, Promote);
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AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
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setOperationAction(ISD::STORE, MVT::v4f32, Promote);
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AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
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setOperationAction(ISD::LOAD, MVT::f32, Promote);
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AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
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setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
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AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
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setOperationAction(ISD::UDIV, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::UREM, MVT::i32, Expand);
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}
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//===---------------------------------------------------------------------===//
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// TargetLowering Callbacks
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//===---------------------------------------------------------------------===//
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SDValue AMDGPUTargetLowering::LowerFormalArguments(
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SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
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InVals.push_back(SDValue());
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}
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return Chain;
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}
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SDValue AMDGPUTargetLowering::LowerReturn(
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SDValue Chain,
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CallingConv::ID CallConv,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc DL, SelectionDAG &DAG) const {
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return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
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}
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//===---------------------------------------------------------------------===//
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// Target specific lowering
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//===---------------------------------------------------------------------===//
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SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
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const {
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switch (Op.getOpcode()) {
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default:
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Op.getNode()->dump();
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assert(0 && "Custom lowering code for this"
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"instruction is not implemented yet!");
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break;
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// AMDIL DAG lowering
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case ISD::SDIV: return LowerSDIV(Op, DAG);
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case ISD::SREM: return LowerSREM(Op, DAG);
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case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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// AMDGPU DAG lowering
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
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}
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return Op;
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}
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SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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DebugLoc DL = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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switch (IntrinsicID) {
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default: return Op;
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case AMDGPUIntrinsic::AMDIL_abs:
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return LowerIntrinsicIABS(Op, DAG);
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case AMDGPUIntrinsic::AMDIL_exp:
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return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
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case AMDGPUIntrinsic::AMDGPU_lrp:
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return LowerIntrinsicLRP(Op, DAG);
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case AMDGPUIntrinsic::AMDIL_fraction:
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return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
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case AMDGPUIntrinsic::AMDIL_mad:
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
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Op.getOperand(2), Op.getOperand(3));
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case AMDGPUIntrinsic::AMDIL_max:
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return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDGPU_imax:
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return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDGPU_umax:
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return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDIL_min:
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return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDGPU_imin:
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return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDGPU_umin:
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return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
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Op.getOperand(2));
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case AMDGPUIntrinsic::AMDIL_round_nearest:
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return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
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}
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}
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///IABS(a) = SMAX(sub(0, a), a)
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SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
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SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
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Op.getOperand(1));
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return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
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}
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/// Linear Interpolation
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/// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
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SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
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SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
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DAG.getConstantFP(1.0f, MVT::f32),
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Op.getOperand(1));
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SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
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Op.getOperand(3));
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1),
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Op.getOperand(2),
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OneSubAC);
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}
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/// \brief Generate Min/Max node
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SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
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SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue True = Op.getOperand(2);
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SDValue False = Op.getOperand(3);
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SDValue CC = Op.getOperand(4);
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if (VT != MVT::f32 ||
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!((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
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return SDValue();
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}
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ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
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switch (CCOpcode) {
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case ISD::SETOEQ:
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case ISD::SETONE:
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case ISD::SETUNE:
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case ISD::SETNE:
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case ISD::SETUEQ:
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case ISD::SETEQ:
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case ISD::SETFALSE:
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case ISD::SETFALSE2:
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case ISD::SETTRUE:
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case ISD::SETTRUE2:
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case ISD::SETUO:
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case ISD::SETO:
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assert(0 && "Operation should already be optimised !");
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case ISD::SETULE:
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case ISD::SETULT:
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case ISD::SETOLE:
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case ISD::SETOLT:
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case ISD::SETLE:
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case ISD::SETLT: {
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if (LHS == True)
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return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
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else
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return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
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}
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case ISD::SETGT:
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case ISD::SETGE:
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case ISD::SETUGE:
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case ISD::SETOGE:
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case ISD::SETUGT:
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case ISD::SETOGT: {
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if (LHS == True)
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return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
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else
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return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
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}
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case ISD::SETCC_INVALID:
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assert(0 && "Invalid setcc condcode !");
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}
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return Op;
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}
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SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
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SelectionDAG &DAG) const {
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DebugLoc DL = Op.getDebugLoc();
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EVT VT = Op.getValueType();
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SDValue Num = Op.getOperand(0);
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SDValue Den = Op.getOperand(1);
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SmallVector<SDValue, 8> Results;
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// RCP = URECIP(Den) = 2^32 / Den + e
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// e is rounding error.
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SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
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// RCP_LO = umulo(RCP, Den) */
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SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
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// RCP_HI = mulhu (RCP, Den) */
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SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
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// NEG_RCP_LO = -RCP_LO
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SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
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RCP_LO);
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// ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
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SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
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NEG_RCP_LO, RCP_LO,
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ISD::SETEQ);
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// Calculate the rounding error from the URECIP instruction
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// E = mulhu(ABS_RCP_LO, RCP)
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SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
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// RCP_A_E = RCP + E
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SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
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// RCP_S_E = RCP - E
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SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
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// Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
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SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
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RCP_A_E, RCP_S_E,
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ISD::SETEQ);
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// Quotient = mulhu(Tmp0, Num)
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SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
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// Num_S_Remainder = Quotient * Den
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SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
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// Remainder = Num - Num_S_Remainder
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SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
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// Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
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SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
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DAG.getConstant(-1, VT),
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DAG.getConstant(0, VT),
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ISD::SETGE);
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// Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
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SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
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DAG.getConstant(0, VT),
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DAG.getConstant(-1, VT),
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DAG.getConstant(0, VT),
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ISD::SETGE);
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// Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
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SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
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Remainder_GE_Zero);
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// Calculate Division result:
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// Quotient_A_One = Quotient + 1
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SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
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DAG.getConstant(1, VT));
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// Quotient_S_One = Quotient - 1
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SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
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DAG.getConstant(1, VT));
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// Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
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SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
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Quotient, Quotient_A_One, ISD::SETEQ);
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// Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
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Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
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Quotient_S_One, Div, ISD::SETEQ);
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// Calculate Rem result:
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// Remainder_S_Den = Remainder - Den
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SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
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// Remainder_A_Den = Remainder + Den
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SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
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// Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
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SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
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Remainder, Remainder_S_Den, ISD::SETEQ);
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// Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
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Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
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Remainder_A_Den, Rem, ISD::SETEQ);
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SDValue Ops[2];
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Ops[0] = Div;
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Ops[1] = Rem;
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return DAG.getMergeValues(Ops, 2, DL);
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}
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//===----------------------------------------------------------------------===//
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// Helper functions
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//===----------------------------------------------------------------------===//
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bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
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if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
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return CFP->isExactlyValue(1.0);
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}
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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return C->isAllOnesValue();
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}
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return false;
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}
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bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
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if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
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return CFP->getValueAPF().isZero();
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}
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
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return C->isNullValue();
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}
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return false;
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}
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SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned VirtualRegister;
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if (!MRI.isLiveIn(Reg)) {
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VirtualRegister = MRI.createVirtualRegister(RC);
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MRI.addLiveIn(Reg, VirtualRegister);
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} else {
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VirtualRegister = MRI.getLiveInVirtReg(Reg);
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}
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return DAG.getRegister(VirtualRegister, VT);
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}
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#define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
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const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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// AMDIL DAG nodes
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NODE_NAME_CASE(MAD);
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NODE_NAME_CASE(CALL);
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NODE_NAME_CASE(UMUL);
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NODE_NAME_CASE(DIV_INF);
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NODE_NAME_CASE(RET_FLAG);
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NODE_NAME_CASE(BRANCH_COND);
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// AMDGPU DAG nodes
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NODE_NAME_CASE(DWORDADDR)
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NODE_NAME_CASE(FRACT)
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NODE_NAME_CASE(FMAX)
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NODE_NAME_CASE(SMAX)
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NODE_NAME_CASE(UMAX)
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NODE_NAME_CASE(FMIN)
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NODE_NAME_CASE(SMIN)
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NODE_NAME_CASE(UMIN)
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NODE_NAME_CASE(URECIP)
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NODE_NAME_CASE(EXPORT)
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NODE_NAME_CASE(CONST_ADDRESS)
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NODE_NAME_CASE(REGISTER_LOAD)
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NODE_NAME_CASE(REGISTER_STORE)
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}
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}
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