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https://github.com/c64scene-ar/llvm-6502.git
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Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221534 91177308-0d34-0410-b5e6-96231b3b80d8
91 lines
2.8 KiB
LLVM
91 lines
2.8 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
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; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s
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; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6 -check-prefix=MIPS32-GT-R1 %s
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; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
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; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
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; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s
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; Prefixes:
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; ALL - All
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; MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's)
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; MIPS64-GT-R1 - MIPS64r1 and above
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define i32 @ctlz_i32(i32 signext %X) nounwind readnone {
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entry:
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; ALL-LABEL: ctlz_i32:
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; MIPS4-NOT: clz
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; MIPS32-GT-R1: clz $2, $4
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; MIPS64-GT-R1: clz $2, $4
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%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true)
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ret i32 %tmp1
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}
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declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone
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define i32 @ctlo_i32(i32 signext %X) nounwind readnone {
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entry:
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; ALL-LABEL: ctlo_i32:
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; MIPS4-NOT: clo
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; MIPS32-GT-R1: clo $2, $4
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; MIPS64-GT-R1: clo $2, $4
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%neg = xor i32 %X, -1
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%tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true)
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ret i32 %tmp1
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}
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define i64 @ctlz_i64(i64 %X) nounwind readnone {
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entry:
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; ALL-LABEL: ctlz_i64:
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; MIPS4-NOT: dclz
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; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4
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; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5
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; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
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; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5
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; MIPS32-R6-DAG: seleqz $[[R5:[0-9]+]], $[[R2]], $5
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; MIPS32-R6-DAG: selnez $[[R6:[0-9]+]], $[[R1]], $5
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; MIPS32-R6-DAG: or $2, $[[R6]], $[[R5]]
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; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
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; MIPS64-GT-R1: dclz $2, $4
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
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ret i64 %tmp1
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}
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declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
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define i64 @ctlo_i64(i64 %X) nounwind readnone {
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entry:
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; ALL-LABEL: ctlo_i64:
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; MIPS4-NOT: dclo
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; MIPS32-GT-R1-DAG: clo $[[R0:[0-9]+]], $4
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; MIPS32-GT-R1-DAG: clo $[[R1:[0-9]+]], $5
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; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32
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; MIPS32-GT-R1-DAG: addiu $[[R3:[0-9]+]], $zero, -1
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; MIPS32-GT-R1-DAG: xor $[[R4:[0-9]+]], $5, $[[R3]]
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; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $[[R4]]
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; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]]
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; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]]
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; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]]
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; MIPS32-GT-R1-DAG: addiu $3, $zero, 0
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; MIPS64-GT-R1: dclo $2, $4
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%neg = xor i64 %X, -1
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
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ret i64 %tmp1
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}
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