mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
7bc8414ee9
Only Linux is supported at the moment, and other platforms quickly fault. As a result these tests would fail on non-Linux hosts. It may be worth making the tests more generic again as more platforms are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174170 91177308-0d34-0410-b5e6-96231b3b80d8
296 lines
8.5 KiB
LLVM
296 lines
8.5 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
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@var32 = global i32 0
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@var64 = global i64 0
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define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_lsl_arith:
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%rhs1 = load volatile i32* @var32
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%shift1 = shl i32 %rhs1, 18
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%val1 = add i32 %lhs32, %shift1
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store volatile i32 %val1, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #18
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%rhs2 = load volatile i32* @var32
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%shift2 = shl i32 %rhs2, 31
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%val2 = add i32 %shift2, %lhs32
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store volatile i32 %val2, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
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%rhs3 = load volatile i32* @var32
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%shift3 = shl i32 %rhs3, 5
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%val3 = sub i32 %lhs32, %shift3
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store volatile i32 %val3, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #5
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; Subtraction is not commutative!
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%rhs4 = load volatile i32* @var32
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%shift4 = shl i32 %rhs4, 19
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%val4 = sub i32 %shift4, %lhs32
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store volatile i32 %val4, i32* @var32
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; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #19
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%lhs4a = load volatile i32* @var32
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%shift4a = shl i32 %lhs4a, 15
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%val4a = sub i32 0, %shift4a
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store volatile i32 %val4a, i32* @var32
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; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsl #15
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%rhs5 = load volatile i64* @var64
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%shift5 = shl i64 %rhs5, 18
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%val5 = add i64 %lhs64, %shift5
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store volatile i64 %val5, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #18
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%rhs6 = load volatile i64* @var64
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%shift6 = shl i64 %rhs6, 31
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%val6 = add i64 %shift6, %lhs64
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store volatile i64 %val6, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #31
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%rhs7 = load volatile i64* @var64
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%shift7 = shl i64 %rhs7, 5
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%val7 = sub i64 %lhs64, %shift7
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store volatile i64 %val7, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #5
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; Subtraction is not commutative!
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%rhs8 = load volatile i64* @var64
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%shift8 = shl i64 %rhs8, 19
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%val8 = sub i64 %shift8, %lhs64
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store volatile i64 %val8, i64* @var64
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; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #19
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%lhs8a = load volatile i64* @var64
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%shift8a = shl i64 %lhs8a, 60
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%val8a = sub i64 0, %shift8a
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store volatile i64 %val8a, i64* @var64
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; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsl #60
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ret void
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; CHECK: ret
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}
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define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_lsr_arith:
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%shift1 = lshr i32 %rhs32, 18
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%val1 = add i32 %lhs32, %shift1
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store volatile i32 %val1, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #18
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%shift2 = lshr i32 %rhs32, 31
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%val2 = add i32 %shift2, %lhs32
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store volatile i32 %val2, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #31
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%shift3 = lshr i32 %rhs32, 5
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%val3 = sub i32 %lhs32, %shift3
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store volatile i32 %val3, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #5
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; Subtraction is not commutative!
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%shift4 = lshr i32 %rhs32, 19
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%val4 = sub i32 %shift4, %lhs32
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store volatile i32 %val4, i32* @var32
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; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #19
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%shift4a = lshr i32 %lhs32, 15
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%val4a = sub i32 0, %shift4a
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store volatile i32 %val4a, i32* @var32
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; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsr #15
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%shift5 = lshr i64 %rhs64, 18
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%val5 = add i64 %lhs64, %shift5
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store volatile i64 %val5, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #18
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%shift6 = lshr i64 %rhs64, 31
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%val6 = add i64 %shift6, %lhs64
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store volatile i64 %val6, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #31
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%shift7 = lshr i64 %rhs64, 5
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%val7 = sub i64 %lhs64, %shift7
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store volatile i64 %val7, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #5
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; Subtraction is not commutative!
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%shift8 = lshr i64 %rhs64, 19
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%val8 = sub i64 %shift8, %lhs64
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store volatile i64 %val8, i64* @var64
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; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #19
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%shift8a = lshr i64 %lhs64, 45
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%val8a = sub i64 0, %shift8a
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store volatile i64 %val8a, i64* @var64
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; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsr #45
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ret void
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; CHECK: ret
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}
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define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_asr_arith:
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%shift1 = ashr i32 %rhs32, 18
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%val1 = add i32 %lhs32, %shift1
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store volatile i32 %val1, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #18
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%shift2 = ashr i32 %rhs32, 31
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%val2 = add i32 %shift2, %lhs32
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store volatile i32 %val2, i32* @var32
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #31
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%shift3 = ashr i32 %rhs32, 5
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%val3 = sub i32 %lhs32, %shift3
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store volatile i32 %val3, i32* @var32
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; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #5
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; Subtraction is not commutative!
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%shift4 = ashr i32 %rhs32, 19
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%val4 = sub i32 %shift4, %lhs32
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store volatile i32 %val4, i32* @var32
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; CHECK-NOT: sub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, asr #19
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%shift4a = ashr i32 %lhs32, 15
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%val4a = sub i32 0, %shift4a
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store volatile i32 %val4a, i32* @var32
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; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, asr #15
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%shift5 = ashr i64 %rhs64, 18
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%val5 = add i64 %lhs64, %shift5
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store volatile i64 %val5, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #18
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%shift6 = ashr i64 %rhs64, 31
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%val6 = add i64 %shift6, %lhs64
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store volatile i64 %val6, i64* @var64
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; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #31
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%shift7 = ashr i64 %rhs64, 5
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%val7 = sub i64 %lhs64, %shift7
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store volatile i64 %val7, i64* @var64
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; CHECK: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #5
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; Subtraction is not commutative!
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%shift8 = ashr i64 %rhs64, 19
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%val8 = sub i64 %shift8, %lhs64
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store volatile i64 %val8, i64* @var64
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; CHECK-NOT: sub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, asr #19
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%shift8a = ashr i64 %lhs64, 45
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%val8a = sub i64 0, %shift8a
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store volatile i64 %val8a, i64* @var64
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; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, asr #45
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ret void
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; CHECK: ret
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}
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define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_cmp:
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%shift1 = shl i32 %rhs32, 13
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%tst1 = icmp uge i32 %lhs32, %shift1
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br i1 %tst1, label %t2, label %end
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; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, lsl #13
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t2:
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%shift2 = lshr i32 %rhs32, 20
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%tst2 = icmp ne i32 %lhs32, %shift2
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br i1 %tst2, label %t3, label %end
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; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, lsr #20
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t3:
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%shift3 = ashr i32 %rhs32, 9
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%tst3 = icmp ne i32 %lhs32, %shift3
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br i1 %tst3, label %t4, label %end
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; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, asr #9
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t4:
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%shift4 = shl i64 %rhs64, 43
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%tst4 = icmp uge i64 %lhs64, %shift4
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br i1 %tst4, label %t5, label %end
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; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, lsl #43
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t5:
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%shift5 = lshr i64 %rhs64, 20
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%tst5 = icmp ne i64 %lhs64, %shift5
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br i1 %tst5, label %t6, label %end
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; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, lsr #20
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t6:
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%shift6 = ashr i64 %rhs64, 59
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%tst6 = icmp ne i64 %lhs64, %shift6
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br i1 %tst6, label %t7, label %end
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; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, asr #59
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t7:
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ret i32 1
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end:
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ret i32 0
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; CHECK: ret
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}
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define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
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; CHECK: test_cmn:
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%shift1 = shl i32 %rhs32, 13
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%val1 = sub i32 0, %shift1
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%tst1 = icmp uge i32 %lhs32, %val1
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br i1 %tst1, label %t2, label %end
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; Important that this isn't lowered to a cmn instruction because if %rhs32 ==
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; 0 then the results will differ.
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; CHECK: sub [[RHS:w[0-9]+]], wzr, {{w[0-9]+}}, lsl #13
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; CHECK: cmp {{w[0-9]+}}, [[RHS]]
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t2:
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%shift2 = lshr i32 %rhs32, 20
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%val2 = sub i32 0, %shift2
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%tst2 = icmp ne i32 %lhs32, %val2
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br i1 %tst2, label %t3, label %end
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; CHECK: cmn {{w[0-9]+}}, {{w[0-9]+}}, lsr #20
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t3:
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%shift3 = ashr i32 %rhs32, 9
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%val3 = sub i32 0, %shift3
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%tst3 = icmp eq i32 %lhs32, %val3
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br i1 %tst3, label %t4, label %end
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; CHECK: cmn {{w[0-9]+}}, {{w[0-9]+}}, asr #9
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t4:
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%shift4 = shl i64 %rhs64, 43
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%val4 = sub i64 0, %shift4
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%tst4 = icmp slt i64 %lhs64, %val4
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br i1 %tst4, label %t5, label %end
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; Again, it's important that cmn isn't used here in case %rhs64 == 0.
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; CHECK: sub [[RHS:x[0-9]+]], xzr, {{x[0-9]+}}, lsl #43
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; CHECK: cmp {{x[0-9]+}}, [[RHS]]
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t5:
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%shift5 = lshr i64 %rhs64, 20
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%val5 = sub i64 0, %shift5
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%tst5 = icmp ne i64 %lhs64, %val5
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br i1 %tst5, label %t6, label %end
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; CHECK: cmn {{x[0-9]+}}, {{x[0-9]+}}, lsr #20
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t6:
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%shift6 = ashr i64 %rhs64, 59
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%val6 = sub i64 0, %shift6
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%tst6 = icmp ne i64 %lhs64, %val6
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br i1 %tst6, label %t7, label %end
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; CHECK: cmn {{x[0-9]+}}, {{x[0-9]+}}, asr #59
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t7:
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ret i32 1
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end:
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ret i32 0
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; CHECK: ret
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}
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