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fddb7667ca
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
69 lines
2.4 KiB
TableGen
69 lines
2.4 KiB
TableGen
//===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "llvm/Target/Target.td"
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//Alpha is little endian
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//===----------------------------------------------------------------------===//
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// Subtarget Features
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//===----------------------------------------------------------------------===//
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def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true",
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"Enable CIX extentions">;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "AlphaRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Calling Convention Description
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//===----------------------------------------------------------------------===//
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include "AlphaCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Schedule Description
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//===----------------------------------------------------------------------===//
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include "AlphaSchedule.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "AlphaInstrInfo.td"
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def AlphaInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Alpha Processor Definitions
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//===----------------------------------------------------------------------===//
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def : Processor<"generic", Alpha21264Itineraries, []>;
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def : Processor<"ev6" , Alpha21264Itineraries, []>;
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def : Processor<"ev67" , Alpha21264Itineraries, [FeatureCIX]>;
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//===----------------------------------------------------------------------===//
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// The Alpha Target
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//===----------------------------------------------------------------------===//
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def Alpha : Target {
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// Pull in Instruction Info:
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let InstructionSet = AlphaInstrInfo;
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}
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