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57e6b2d1f3
Merge consecutive if-regions if they contain identical statements. Both transformations reduce number of branches. The transformation is guarded by a target-hook, and is currently enabled only for +R600, but the correctness has been tested on X86 target using a variety of CPU benchmarks. Patch by: Mei Ye git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187278 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
2.3 KiB
C++
72 lines
2.3 KiB
C++
//===-- AMDGPUTargetMachine.h - AMDGPU TargetMachine Interface --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief The AMDGPU TargetMachine interface definition for hw codgen targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDGPU_TARGET_MACHINE_H
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#define AMDGPU_TARGET_MACHINE_H
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#include "AMDGPUFrameLowering.h"
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#include "AMDGPUInstrInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "AMDILIntrinsicInfo.h"
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#include "R600ISelLowering.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/IR/DataLayout.h"
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namespace llvm {
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class AMDGPUTargetMachine : public LLVMTargetMachine {
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AMDGPUSubtarget Subtarget;
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const DataLayout Layout;
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AMDGPUFrameLowering FrameLowering;
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AMDGPUIntrinsicInfo IntrinsicInfo;
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OwningPtr<AMDGPUInstrInfo> InstrInfo;
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OwningPtr<AMDGPUTargetLowering> TLInfo;
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const InstrItineraryData *InstrItins;
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public:
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AMDGPUTargetMachine(const Target &T, StringRef TT, StringRef FS,
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StringRef CPU, TargetOptions Options, Reloc::Model RM,
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CodeModel::Model CM, CodeGenOpt::Level OL);
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~AMDGPUTargetMachine();
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virtual const AMDGPUFrameLowering *getFrameLowering() const {
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return &FrameLowering;
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}
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virtual const AMDGPUIntrinsicInfo *getIntrinsicInfo() const {
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return &IntrinsicInfo;
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}
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virtual const AMDGPUInstrInfo *getInstrInfo() const {
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return InstrInfo.get();
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}
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virtual const AMDGPUSubtarget *getSubtargetImpl() const { return &Subtarget; }
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virtual const AMDGPURegisterInfo *getRegisterInfo() const {
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return &InstrInfo->getRegisterInfo();
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}
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virtual AMDGPUTargetLowering *getTargetLowering() const {
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return TLInfo.get();
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}
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virtual const InstrItineraryData *getInstrItineraryData() const {
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return InstrItins;
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}
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virtual const DataLayout *getDataLayout() const { return &Layout; }
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virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
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/// \brief Register R600 analysis passes with a pass manager.
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virtual void addAnalysisPasses(PassManagerBase &PM);
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};
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} // End namespace llvm
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#endif // AMDGPU_TARGET_MACHINE_H
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