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https://github.com/c64scene-ar/llvm-6502.git
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24e1b39a24
When a truncate node defines a legal vector type but uses an illegal vector type, the legalization process was splitting the vector until <1 x vector> type, but then it was failing to scalarize the node because it did not know how to handle TRUNCATE. <rdar://problem/14989896> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190830 91177308-0d34-0410-b5e6-96231b3b80d8
247 lines
9.4 KiB
LLVM
247 lines
9.4 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
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; PR7158
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define i32 @test_pr7158() nounwind {
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bb.nph55.bb.nph55.split_crit_edge:
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br label %bb3
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bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge
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br i1 undef, label %bb.i19, label %bb3
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bb.i19: ; preds = %bb.i19, %bb3
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%0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3]
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%1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1]
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%2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0]
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%3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0]
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br label %bb.i19
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}
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; Check that the DAG combiner does not arbitrarily modify BUILD_VECTORs
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; after legalization.
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define void @test_illegal_build_vector() nounwind {
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entry:
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store <2 x i64> undef, <2 x i64>* undef, align 16
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%0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1]
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%1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1]
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store <16 x i8> %1, <16 x i8>* undef, align 16
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ret void
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}
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; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
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; converted back to be used as a vector type.
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; CHECK: test_vmovrrd_combine
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define <4 x i32> @test_vmovrrd_combine() nounwind {
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entry:
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br i1 undef, label %bb1, label %bb2
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bb1:
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%0 = bitcast <2 x i64> zeroinitializer to <2 x double>
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%1 = extractelement <2 x double> %0, i32 0
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%2 = bitcast double %1 to i64
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%3 = insertelement <1 x i64> undef, i64 %2, i32 0
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; CHECK-NOT: vmov s
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; CHECK: vext.8
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%4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
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%tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8>
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%5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
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%tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32>
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br i1 undef, label %bb2, label %bb1
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bb2:
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%result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ]
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ret <4 x i32> %result
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}
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; Test trying to do a ShiftCombine on illegal types.
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; The vector should be split first.
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define void @lshrIllegalType(<8 x i32>* %A) nounwind {
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%tmp1 = load <8 x i32>* %A
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%tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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store <8 x i32> %tmp2, <8 x i32>* %A
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ret void
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}
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; Test folding a binary vector operation with constant BUILD_VECTOR
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; operands with i16 elements.
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define void @test_i16_constant_fold() nounwind optsize {
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entry:
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%0 = sext <4 x i1> zeroinitializer to <4 x i16>
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%1 = add <4 x i16> %0, zeroinitializer
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%2 = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%3 = add <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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%4 = trunc <8 x i16> %3 to <8 x i8>
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tail call void @llvm.arm.neon.vst1.v8i8(i8* undef, <8 x i8> %4, i32 1)
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unreachable
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}
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declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind
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; Test that loads and stores of i64 vector elements are handled as f64 values
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; so they are not split up into i32 values. Radar 8755338.
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define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind {
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; CHECK: i64_buildvector
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; CHECK: vldr
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%t0 = load i64* %ptr, align 4
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%t1 = insertelement <2 x i64> undef, i64 %t0, i32 0
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store <2 x i64> %t1, <2 x i64>* %vp
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ret void
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}
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define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind {
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; CHECK: i64_insertelement
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; CHECK: vldr
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%t0 = load i64* %ptr, align 4
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%vec = load <2 x i64>* %vp
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%t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0
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store <2 x i64> %t1, <2 x i64>* %vp
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ret void
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}
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define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
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; CHECK: i64_extractelement
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; CHECK: vstr
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%vec = load <2 x i64>* %vp
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%t1 = extractelement <2 x i64> %vec, i32 0
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store i64 %t1, i64* %ptr
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ret void
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}
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; Test trying to do a AND Combine on illegal types.
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define void @andVec(<3 x i8>* %A) nounwind {
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%tmp = load <3 x i8>* %A, align 4
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%and = and <3 x i8> %tmp, <i8 7, i8 7, i8 7>
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store <3 x i8> %and, <3 x i8>* %A
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ret void
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}
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; Test trying to do an OR Combine on illegal types.
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define void @orVec(<3 x i8>* %A) nounwind {
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%tmp = load <3 x i8>* %A, align 4
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%or = or <3 x i8> %tmp, <i8 7, i8 7, i8 7>
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store <3 x i8> %or, <3 x i8>* %A
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ret void
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}
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; The following test was hitting an assertion in the DAG combiner when
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; constant folding the multiply because the "sext undef" was translated to
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; a BUILD_VECTOR with i32 0 operands, which did not match the i16 operands
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; of the other BUILD_VECTOR.
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define i16 @foldBuildVectors() {
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%1 = sext <8 x i8> undef to <8 x i16>
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%2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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%3 = extractelement <8 x i16> %2, i32 0
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ret i16 %3
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}
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; Test that we are generating vrev and vext for reverse shuffles of v8i16
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; shuffles.
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; CHECK: reverse_v8i16
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define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) {
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%v0 = load <8 x i16>* %loadaddr
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; CHECK: vrev64.16
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; CHECK: vext.16
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%v1 = shufflevector <8 x i16> %v0, <8 x i16> undef,
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<8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
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store <8 x i16> %v1, <8 x i16>* %storeaddr
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ret void
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}
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; Test that we are generating vrev and vext for reverse shuffles of v16i8
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; shuffles.
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; CHECK: reverse_v16i8
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define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) {
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%v0 = load <16 x i8>* %loadaddr
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; CHECK: vrev64.8
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; CHECK: vext.8
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%v1 = shufflevector <16 x i8> %v0, <16 x i8> undef,
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<16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8,
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i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
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store <16 x i8> %v1, <16 x i8>* %storeaddr
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ret void
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}
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; <rdar://problem/14170854>.
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; vldr cannot handle unaligned loads.
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; Fall back to vld1.32, which can, instead of using the general purpose loads
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; followed by a costly sequence of instructions to build the vector register.
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; CHECK: t3
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; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}
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; CHECK: vld1.32 {[[REG]][1]}
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; CHECK: vmull.u8 q{{[0-9]+}}, [[REG]], [[REG]]
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define <8 x i16> @t3(i8 zeroext %xf, i8* nocapture %sp0, i8* nocapture %sp1, i32* nocapture %outp) {
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entry:
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%pix_sp0.0.cast = bitcast i8* %sp0 to i32*
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%pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1
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%pix_sp1.0.cast = bitcast i8* %sp1 to i32*
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%pix_sp1.0.copyload = load i32* %pix_sp1.0.cast, align 1
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%vecinit = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
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%vecinit1 = insertelement <2 x i32> %vecinit, i32 %pix_sp1.0.copyload, i32 1
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%0 = bitcast <2 x i32> %vecinit1 to <8 x i8>
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%vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %0)
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ret <8 x i16> %vmull.i
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}
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; Function Attrs: nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>)
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; Check that (insert_vector_elt (load)) => (vector_load).
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; Thus, check that scalar_to_vector do not interfer with that.
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define <8 x i16> @t4(i8* nocapture %sp0) {
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; CHECK: t4
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; CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r0]
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entry:
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%pix_sp0.0.cast = bitcast i8* %sp0 to i32*
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%pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1
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%vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 0
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%0 = bitcast <2 x i32> %vec to <8 x i8>
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%vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %0)
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ret <8 x i16> %vmull.i
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}
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; Make sure vector load is used for all three loads.
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; Lowering to build vector was breaking the single use property of the load of
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; %pix_sp0.0.copyload.
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; CHECK: t5
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; CHECK: vld1.32 {[[REG1:d[0-9]+]][1]}, [r0]
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; CHECK: vorr [[REG2:d[0-9]+]], [[REG1]], [[REG1]]
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; CHECK: vld1.32 {[[REG1]][0]}, [r1]
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; CHECK: vld1.32 {[[REG2]][0]}, [r2]
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; CHECK: vmull.u8 q{{[0-9]+}}, [[REG1]], [[REG2]]
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define <8 x i16> @t5(i8* nocapture %sp0, i8* nocapture %sp1, i8* nocapture %sp2) {
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entry:
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%pix_sp0.0.cast = bitcast i8* %sp0 to i32*
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%pix_sp0.0.copyload = load i32* %pix_sp0.0.cast, align 1
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%pix_sp1.0.cast = bitcast i8* %sp1 to i32*
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%pix_sp1.0.copyload = load i32* %pix_sp1.0.cast, align 1
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%pix_sp2.0.cast = bitcast i8* %sp2 to i32*
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%pix_sp2.0.copyload = load i32* %pix_sp2.0.cast, align 1
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%vec = insertelement <2 x i32> undef, i32 %pix_sp0.0.copyload, i32 1
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%vecinit1 = insertelement <2 x i32> %vec, i32 %pix_sp1.0.copyload, i32 0
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%vecinit2 = insertelement <2 x i32> %vec, i32 %pix_sp2.0.copyload, i32 0
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%0 = bitcast <2 x i32> %vecinit1 to <8 x i8>
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%1 = bitcast <2 x i32> %vecinit2 to <8 x i8>
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%vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %1)
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ret <8 x i16> %vmull.i
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}
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; <rdar://problem/14989896> Make sure we manage to truncate a vector from an
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; illegal type to a legal type.
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define <2 x i8> @test_truncate(<2 x i128> %in) {
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; CHECK-LABEL: test_truncate:
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; CHECK: mov [[BASE:r[0-9]+]], sp
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; CHECK-NEXT: vld1.32 {[[REG1:d[0-9]+]][0]}, {{\[}}[[BASE]]:32]
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; CHECK-NEXT: add [[BASE2:r[0-9]+]], [[BASE]], #4
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; CHECK-NEXT: vld1.32 {[[REG1]][1]}, {{\[}}[[BASE2]]:32]
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; REG2 Should map on the same Q register as REG1, i.e., REG2 = REG1 - 1, but we
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; cannot express that.
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; CHECK-NEXT: vmov.32 [[REG2:d[0-9]+]][0], r0
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; CHECK-NEXT: vmov.32 [[REG2]][1], r1
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; The Q register used here should match floor(REG1/2), but we cannot express that.
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; CHECK-NEXT: vmovn.i64 [[RES:d[0-9]+]], q{{[0-9]+}}
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; CHECK-NEXT: vmov r0, r1, [[RES]]
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entry:
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%res = trunc <2 x i128> %in to <2 x i8>
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ret <2 x i8> %res
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}
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