Silviu Baranga a210db781f Enabling the generation of dependency breakers for partial updates on Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178134 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-27 12:38:44 +00:00
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AArch64	Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings	2013-03-26 18:56:54 +00:00
ARM	Enabling the generation of dependency breakers for partial updates on Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32.	2013-03-27 12:38:44 +00:00
CPP	test commit: remove blank line.	2013-03-14 05:43:59 +00:00
Generic	XFAIL some of the generic CodeGen tests for Hexagon.	2013-03-25 21:04:16 +00:00
Hexagon	Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.	2013-03-26 15:43:57 +00:00
Inputs	Adding DIImportedModules to DIScopes.	2013-03-27 00:07:26 +00:00
MBlaze	Remove unnecessary leading comment characters in lit-only file	2013-03-18 22:08:16 +00:00
Mips	Remove unnecessary leading comment characters in lit-only file	2013-03-18 22:08:16 +00:00
MSP430	Remove unnecessary leading comment characters in lit-only file	2013-03-18 22:08:16 +00:00
NVPTX	[NVPTX] Fix handling of vector arguments	2013-03-24 21:17:47 +00:00
PowerPC	Allocate r0 on PPC	2013-03-27 06:52:27 +00:00
R600	R600/SI: add cummuting of rev instructions	2013-03-27 09:12:59 +00:00
SI
SPARC	Remove unnecessary leading comment characters in lit-only file	2013-03-18 22:08:16 +00:00
Thumb	Adding DIImportedModules to DIScopes.	2013-03-27 00:07:26 +00:00
Thumb2	SDAG: Handle scalarizing an extend of a <1 x iN> vector.	2013-03-07 05:47:54 +00:00
X86	Adding DIImportedModules to DIScopes.	2013-03-27 00:07:26 +00:00
XCore	Remove unnecessary leading comment characters in lit-only file	2013-03-18 22:08:16 +00:00