mirror of
https://github.com/c64scene-ar/llvm-6502.git
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64d80e3387
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
3.2 KiB
TableGen
115 lines
3.2 KiB
TableGen
//===- SparcInstrFormats.td - Sparc Instruction Formats ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
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field bits<32> Inst;
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let Namespace = "SP";
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bits<2> op;
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let Inst{31-30} = op; // Top two bits are the 'op' field
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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//===----------------------------------------------------------------------===//
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// Format #2 instruction classes in the Sparc
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//===----------------------------------------------------------------------===//
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// Format 2 instructions
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class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSP<outs, ins, asmstr, pattern> {
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bits<3> op2;
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bits<22> imm22;
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let op = 0; // op = 0
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let Inst{24-22} = op2;
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let Inst{21-0} = imm22;
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}
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// Specific F2 classes: SparcV8 manual, page 44
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//
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class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
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: F2<outs, ins, asmstr, pattern> {
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bits<5> rd;
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let op2 = op2Val;
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let Inst{29-25} = rd;
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}
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class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr,
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list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
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bits<4> cond;
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bit annul = 0; // currently unused
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let cond = condVal;
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let op2 = op2Val;
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let Inst{29} = annul;
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let Inst{28-25} = cond;
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}
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//===----------------------------------------------------------------------===//
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// Format #3 instruction classes in the Sparc
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//===----------------------------------------------------------------------===//
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class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstSP<outs, ins, asmstr, pattern> {
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bits<5> rd;
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bits<6> op3;
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bits<5> rs1;
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let op{1} = 1; // Op = 2 or 3
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let Inst{29-25} = rd;
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let Inst{24-19} = op3;
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let Inst{18-14} = rs1;
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}
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// Specific F3 classes: SparcV8 manual, page 44
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//
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class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<8> asi = 0; // asi not currently used
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 0; // i field = 0
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let Inst{12-5} = asi; // address space identifier
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let Inst{4-0} = rs2;
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}
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class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<13> simm13;
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let op = opVal;
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let op3 = op3val;
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let Inst{13} = 1; // i field = 1
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let Inst{12-0} = simm13;
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}
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// floating-point
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class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins,
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string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
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bits<5> rs2;
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let op = opVal;
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let op3 = op3val;
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let Inst{13-5} = opfval; // fp opcode
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let Inst{4-0} = rs2;
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}
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