mirror of
https://github.com/c64scene-ar/llvm-6502.git
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fe2b8b1960
Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221534 91177308-0d34-0410-b5e6-96231b3b80d8
173 lines
8.0 KiB
LLVM
173 lines
8.0 KiB
LLVM
; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
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; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
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; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
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; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
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; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
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; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s
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; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
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; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s
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; Test the integer arguments for all ABI's and byte orders as specified by
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; section 5 of MD00305 (MIPS ABIs Described).
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;
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; N32/N64 are identical in this area so their checks have been combined into
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; the 'NEW' prefix (the N stands for New).
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;
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; Varargs are covered in arguments-hard-float-varargs.ll.
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@bytes = global [11 x i8] zeroinitializer
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@dwords = global [11 x i64] zeroinitializer
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@floats = global [11 x float] zeroinitializer
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@doubles = global [11 x double] zeroinitializer
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define void @align_to_arg_slots(i8 signext %a, i8 signext %b, i8 signext %c,
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i8 signext %d, i8 signext %e, i8 signext %f,
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i8 signext %g, i8 signext %h, i8 signext %i,
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i8 signext %j) nounwind {
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entry:
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%0 = getelementptr [11 x i8]* @bytes, i32 0, i32 1
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store volatile i8 %a, i8* %0
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%1 = getelementptr [11 x i8]* @bytes, i32 0, i32 2
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store volatile i8 %b, i8* %1
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%2 = getelementptr [11 x i8]* @bytes, i32 0, i32 3
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store volatile i8 %c, i8* %2
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%3 = getelementptr [11 x i8]* @bytes, i32 0, i32 4
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store volatile i8 %d, i8* %3
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%4 = getelementptr [11 x i8]* @bytes, i32 0, i32 5
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store volatile i8 %e, i8* %4
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%5 = getelementptr [11 x i8]* @bytes, i32 0, i32 6
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store volatile i8 %f, i8* %5
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%6 = getelementptr [11 x i8]* @bytes, i32 0, i32 7
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store volatile i8 %g, i8* %6
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%7 = getelementptr [11 x i8]* @bytes, i32 0, i32 8
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store volatile i8 %h, i8* %7
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%8 = getelementptr [11 x i8]* @bytes, i32 0, i32 9
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store volatile i8 %i, i8* %8
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%9 = getelementptr [11 x i8]* @bytes, i32 0, i32 10
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store volatile i8 %j, i8* %9
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ret void
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}
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; ALL-LABEL: align_to_arg_slots:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
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; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)(
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; The first four arguments are the same in O32/N32/N64
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; ALL-DAG: sb $4, 1([[R1]])
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; ALL-DAG: sb $5, 2([[R1]])
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; ALL-DAG: sb $6, 3([[R1]])
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; ALL-DAG: sb $7, 4([[R1]])
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; N32/N64 get an extra four arguments in registers
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; O32 starts loading from the stack. The addresses start at 16 because space is
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; always reserved for the first four arguments.
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; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp)
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; O32-DAG: sb [[R3]], 5([[R1]])
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; NEW-DAG: sb $8, 5([[R1]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 20($sp)
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; O32-DAG: sb [[R3]], 6([[R1]])
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; NEW-DAG: sb $9, 6([[R1]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 24($sp)
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; O32-DAG: sb [[R3]], 7([[R1]])
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; NEW-DAG: sb $10, 7([[R1]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 28($sp)
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; O32-DAG: sb [[R3]], 8([[R1]])
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; NEW-DAG: sb $11, 8([[R1]])
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; O32/N32/N64 are accessing the stack at this point.
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; Unlike O32, N32/N64 do not reserve space for the arguments.
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; increase by 4 for O32 and 8 for N32/N64.
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; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)
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; O32-DAG: sb [[R3]], 9([[R1]])
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; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)
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; NEW-DAG: sb [[R3]], 9([[R1]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 36($sp)
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; O32-DAG: sb [[R3]], 10([[R1]])
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; NEW-DAG: ld [[R3:\$[0-9]+]], 8($sp)
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; NEW-DAG: sb [[R3]], 10([[R1]])
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define void @slot_skipping(i8 signext %a, i64 signext %b, i8 signext %c,
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i8 signext %d, i8 signext %e, i8 signext %f,
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i8 signext %g, i64 signext %i, i8 signext %j) nounwind {
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entry:
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%0 = getelementptr [11 x i8]* @bytes, i32 0, i32 1
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store volatile i8 %a, i8* %0
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%1 = getelementptr [11 x i64]* @dwords, i32 0, i32 1
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store volatile i64 %b, i64* %1
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%2 = getelementptr [11 x i8]* @bytes, i32 0, i32 2
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store volatile i8 %c, i8* %2
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%3 = getelementptr [11 x i8]* @bytes, i32 0, i32 3
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store volatile i8 %d, i8* %3
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%4 = getelementptr [11 x i8]* @bytes, i32 0, i32 4
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store volatile i8 %e, i8* %4
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%5 = getelementptr [11 x i8]* @bytes, i32 0, i32 5
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store volatile i8 %f, i8* %5
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%6 = getelementptr [11 x i8]* @bytes, i32 0, i32 6
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store volatile i8 %g, i8* %6
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%7 = getelementptr [11 x i64]* @dwords, i32 0, i32 2
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store volatile i64 %i, i64* %7
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%8 = getelementptr [11 x i8]* @bytes, i32 0, i32 7
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store volatile i8 %j, i8* %8
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ret void
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}
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; ALL-LABEL: slot_skipping:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
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; SYM64-DAG: ld [[R1:\$[0-9]+]], %got_disp(bytes)(
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; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(dwords)
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; SYM64-DAG: ld [[R2:\$[0-9]+]], %got_disp(dwords)(
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; The first argument is the same in O32/N32/N64.
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; ALL-DAG: sb $4, 1([[R1]])
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; The second slot is insufficiently aligned for i64 on O32 so it is skipped.
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; Also, i64 occupies two slots on O32 and only one for N32/N64.
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; O32-DAG: sw $6, 8([[R2]])
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; O32-DAG: sw $7, 12([[R2]])
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; NEW-DAG: sd $5, 8([[R2]])
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; N32/N64 get an extra four arguments in registers and still have two left from
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; the first four.
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; O32 starts loading from the stack. The addresses start at 16 because space is
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; always reserved for the first four arguments.
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; It's not clear why O32 uses lbu for this argument, but it's not wrong so we'll
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; accept it for now. The only IR difference is that this argument has
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; anyext from i8 and align 8 on it.
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; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp)
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; O32-DAG: sb [[R3]], 2([[R1]])
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; NEW-DAG: sb $6, 2([[R1]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 20($sp)
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; O32-DAG: sb [[R3]], 3([[R1]])
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; NEW-DAG: sb $7, 3([[R1]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 24($sp)
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; O32-DAG: sb [[R3]], 4([[R1]])
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; NEW-DAG: sb $8, 4([[R1]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 28($sp)
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; O32-DAG: sb [[R3]], 5([[R1]])
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; NEW-DAG: sb $9, 5([[R1]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)
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; O32-DAG: sb [[R3]], 6([[R1]])
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; NEW-DAG: sb $10, 6([[R1]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 40($sp)
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; O32-DAG: sw [[R3]], 16([[R2]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 44($sp)
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; O32-DAG: sw [[R3]], 20([[R2]])
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; NEW-DAG: sd $11, 16([[R2]])
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; O32/N32/N64 are accessing the stack at this point.
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; Unlike O32, N32/N64 do not reserve space for the arguments.
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; increase by 4 for O32 and 8 for N32/N64.
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; O32-DAG: lw [[R3:\$[0-9]+]], 48($sp)
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; O32-DAG: sb [[R3]], 7([[R1]])
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; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)
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; NEW-DAG: sb [[R3]], 7([[R1]])
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