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1f996fa36b
This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225277 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.9 KiB
LLVM
48 lines
1.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
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; XUN: llc -march=amdgcn -mcpu=SI -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG-SAFE -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone
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declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone
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declare float @llvm.sqrt.f32(float) nounwind readnone
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; FUNC-LABEL: {{^}}rcp_f32:
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; SI: v_rcp_f32_e32
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; EG: RECIP_IEEE
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define void @rcp_f32(float addrspace(1)* %out, float %src) nounwind {
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%rcp = call float @llvm.AMDGPU.rcp.f32(float %src) nounwind readnone
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FIXME: Evergreen only ever does unsafe fp math.
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; FUNC-LABEL: {{^}}rcp_pat_f32:
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; SI-SAFE: v_rcp_f32_e32
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; XSI-SAFE-SPDENORM-NOT: v_rcp_f32_e32
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; EG: RECIP_IEEE
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define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
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%rcp = fdiv float 1.0, %src
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}rsq_rcp_pat_f32:
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; SI-UNSAFE: v_rsq_f32_e32
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; SI-SAFE: v_sqrt_f32_e32
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; SI-SAFE: v_rcp_f32_e32
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; EG: RECIPSQRT_IEEE
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define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind {
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%sqrt = call float @llvm.sqrt.f32(float %src) nounwind readnone
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%rcp = call float @llvm.AMDGPU.rcp.f32(float %sqrt) nounwind readnone
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store float %rcp, float addrspace(1)* %out, align 4
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ret void
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}
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