mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f8c7394781
This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
382 lines
14 KiB
C++
382 lines
14 KiB
C++
//===- InstrInfoEmitter.cpp - Generate a Instruction Set Desc. ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend is responsible for emitting a description of the target
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// instruction set for the code generator.
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//
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//===----------------------------------------------------------------------===//
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#include "InstrInfoEmitter.h"
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#include "CodeGenTarget.h"
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#include "Record.h"
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#include <algorithm>
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#include <iostream>
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using namespace llvm;
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static void PrintDefList(const std::vector<Record*> &Uses,
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unsigned Num, std::ostream &OS) {
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OS << "static const unsigned ImplicitList" << Num << "[] = { ";
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for (unsigned i = 0, e = Uses.size(); i != e; ++i)
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OS << getQualifiedName(Uses[i]) << ", ";
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OS << "0 };\n";
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}
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static void PrintBarriers(std::vector<Record*> &Barriers,
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unsigned Num, std::ostream &OS) {
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OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { ";
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for (unsigned i = 0, e = Barriers.size(); i != e; ++i)
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OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, ";
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OS << "NULL };\n";
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}
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary Information.
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//===----------------------------------------------------------------------===//
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struct RecordNameComparator {
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bool operator()(const Record *Rec1, const Record *Rec2) const {
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return Rec1->getName() < Rec2->getName();
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}
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};
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void InstrInfoEmitter::GatherItinClasses() {
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std::vector<Record*> DefList =
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Records.getAllDerivedDefinitions("InstrItinClass");
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std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
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for (unsigned i = 0, N = DefList.size(); i < N; i++)
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ItinClassMap[DefList[i]->getName()] = i;
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}
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unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
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return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
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}
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//===----------------------------------------------------------------------===//
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// Operand Info Emission.
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//===----------------------------------------------------------------------===//
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std::vector<std::string>
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InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
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std::vector<std::string> Result;
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for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
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// Handle aggregate operands and normal operands the same way by expanding
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// either case into a list of operands for this op.
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std::vector<CodeGenInstruction::OperandInfo> OperandList;
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// This might be a multiple operand thing. Targets like X86 have
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// registers in their multi-operand operands. It may also be an anonymous
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// operand, which has a single operand, but no declared class for the
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// operand.
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DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
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if (!MIOI || MIOI->getNumArgs() == 0) {
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// Single, anonymous, operand.
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OperandList.push_back(Inst.OperandList[i]);
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} else {
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for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
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OperandList.push_back(Inst.OperandList[i]);
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Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
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OperandList.back().Rec = OpR;
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}
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}
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for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
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Record *OpR = OperandList[j].Rec;
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std::string Res;
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if (OpR->isSubClassOf("RegisterClass"))
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Res += getQualifiedName(OpR) + "RegClassID, ";
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else
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Res += "0, ";
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// Fill in applicable flags.
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Res += "0";
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// Ptr value whose register class is resolved via callback.
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if (OpR->getName() == "ptr_rc")
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Res += "|(1<<TOI::LookupPtrRegClass)";
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// Predicate operands. Check to see if the original unexpanded operand
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// was of type PredicateOperand.
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if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
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Res += "|(1<<TOI::Predicate)";
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// Optional def operands. Check to see if the original unexpanded operand
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// was of type OptionalDefOperand.
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if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
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Res += "|(1<<TOI::OptionalDef)";
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// Fill in constraint info.
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Res += ", " + Inst.OperandList[i].Constraints[j];
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Result.push_back(Res);
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}
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}
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return Result;
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}
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void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
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OperandInfoMapTy &OperandInfoIDs) {
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// ID #0 is for no operand info.
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unsigned OperandListNum = 0;
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OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
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OS << "\n";
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const CodeGenTarget &Target = CDP.getTargetInfo();
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
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unsigned &N = OperandInfoIDs[OperandInfo];
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if (N != 0) continue;
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N = ++OperandListNum;
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OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
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for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
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OS << "{ " << OperandInfo[i] << " }, ";
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OS << "};\n";
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}
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}
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void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs,
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const std::vector<CodeGenRegisterClass> &RCs,
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std::vector<Record*> &Barriers) {
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std::set<Record*> DefSet;
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unsigned NumDefs = Defs.size();
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for (unsigned i = 0; i < NumDefs; ++i)
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DefSet.insert(Defs[i]);
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for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
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const CodeGenRegisterClass &RC = RCs[i];
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unsigned NumRegs = RC.Elements.size();
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if (NumRegs > NumDefs)
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continue; // Can't possibly clobber this RC.
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bool Clobber = true;
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for (unsigned j = 0; j < NumRegs; ++j) {
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Record *Reg = RC.Elements[j];
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if (!DefSet.count(Reg)) {
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Clobber = false;
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break;
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}
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}
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if (Clobber)
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Barriers.push_back(RC.TheDef);
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}
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}
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//===----------------------------------------------------------------------===//
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// Main Output.
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//===----------------------------------------------------------------------===//
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// run - Emit the main instruction description records for the target...
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void InstrInfoEmitter::run(std::ostream &OS) {
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GatherItinClasses();
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EmitSourceFileHeader("Target Instruction Descriptors", OS);
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OS << "namespace llvm {\n\n";
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CodeGenTarget &Target = CDP.getTargetInfo();
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const std::string &TargetName = Target.getName();
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Record *InstrInfo = Target.getInstructionSet();
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const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses();
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// Keep track of all of the def lists we have emitted already.
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std::map<std::vector<Record*>, unsigned> EmittedLists;
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unsigned ListNumber = 0;
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std::map<std::vector<Record*>, unsigned> EmittedBarriers;
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unsigned BarrierNumber = 0;
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std::map<Record*, unsigned> BarriersMap;
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// Emit all of the instruction's implicit uses and defs.
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for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
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E = Target.inst_end(); II != E; ++II) {
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Record *Inst = II->second.TheDef;
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std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
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if (!Uses.empty()) {
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unsigned &IL = EmittedLists[Uses];
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if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
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}
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std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
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if (!Defs.empty()) {
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std::vector<Record*> RCBarriers;
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DetectRegisterClassBarriers(Defs, RCs, RCBarriers);
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if (!RCBarriers.empty()) {
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unsigned &IB = EmittedBarriers[RCBarriers];
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if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS);
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BarriersMap.insert(std::make_pair(Inst, IB));
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}
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unsigned &IL = EmittedLists[Defs];
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if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
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}
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}
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OperandInfoMapTy OperandInfoIDs;
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// Emit all of the operand info records.
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EmitOperandInfo(OS, OperandInfoIDs);
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// Emit all of the TargetInstrDesc records in their ENUM ordering.
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//
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OS << "\nstatic const TargetInstrDesc " << TargetName
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<< "Insts[] = {\n";
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std::vector<const CodeGenInstruction*> NumberedInstructions;
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Target.getInstructionsByEnumValue(NumberedInstructions);
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for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
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emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
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BarriersMap, OperandInfoIDs, OS);
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OS << "};\n";
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OS << "} // End llvm namespace \n";
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}
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void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
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Record *InstrInfo,
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std::map<std::vector<Record*>, unsigned> &EmittedLists,
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std::map<Record*, unsigned> &BarriersMap,
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const OperandInfoMapTy &OpInfo,
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std::ostream &OS) {
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int MinOperands = 0;
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if (!Inst.OperandList.empty())
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// Each logical operand can be multiple MI operands.
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MinOperands = Inst.OperandList.back().MIOperandNo +
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Inst.OperandList.back().MINumOperands;
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OS << " { ";
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OS << Num << ",\t" << MinOperands << ",\t"
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<< Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
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<< ",\t\"" << Inst.TheDef->getName() << "\", 0";
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// Emit all of the target indepedent flags...
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if (Inst.isReturn) OS << "|(1<<TID::Return)";
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if (Inst.isBranch) OS << "|(1<<TID::Branch)";
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if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
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if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
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if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
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if (Inst.isCall) OS << "|(1<<TID::Call)";
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if (Inst.canFoldAsLoad) OS << "|(1<<TID::FoldableAsLoad)";
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if (Inst.mayLoad) OS << "|(1<<TID::MayLoad)";
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if (Inst.mayStore) OS << "|(1<<TID::MayStore)";
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if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
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if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
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if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";
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if (Inst.isTerminator) OS << "|(1<<TID::Terminator)";
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if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
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if (Inst.isNotDuplicable) OS << "|(1<<TID::NotDuplicable)";
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if (Inst.hasOptionalDef) OS << "|(1<<TID::HasOptionalDef)";
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if (Inst.usesCustomDAGSchedInserter)
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OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
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if (Inst.isVariadic) OS << "|(1<<TID::Variadic)";
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if (Inst.hasSideEffects) OS << "|(1<<TID::UnmodeledSideEffects)";
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if (Inst.isAsCheapAsAMove) OS << "|(1<<TID::CheapAsAMove)";
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OS << ", 0";
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// Emit all of the target-specific flags...
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ListInit *LI = InstrInfo->getValueAsListInit("TSFlagsFields");
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ListInit *Shift = InstrInfo->getValueAsListInit("TSFlagsShifts");
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if (LI->getSize() != Shift->getSize())
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throw "Lengths of " + InstrInfo->getName() +
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":(TargetInfoFields, TargetInfoPositions) must be equal!";
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for (unsigned i = 0, e = LI->getSize(); i != e; ++i)
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emitShiftedValue(Inst.TheDef, dynamic_cast<StringInit*>(LI->getElement(i)),
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dynamic_cast<IntInit*>(Shift->getElement(i)), OS);
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OS << ", ";
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// Emit the implicit uses and defs lists...
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std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
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if (UseList.empty())
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OS << "NULL, ";
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else
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OS << "ImplicitList" << EmittedLists[UseList] << ", ";
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std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
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if (DefList.empty())
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OS << "NULL, ";
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else
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OS << "ImplicitList" << EmittedLists[DefList] << ", ";
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std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef);
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if (BI == BarriersMap.end())
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OS << "NULL, ";
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else
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OS << "Barriers" << BI->second << ", ";
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// Emit the operand info.
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std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
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if (OperandInfo.empty())
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OS << "0";
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else
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OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
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OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
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}
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void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
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IntInit *ShiftInt, std::ostream &OS) {
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if (Val == 0 || ShiftInt == 0)
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throw std::string("Illegal value or shift amount in TargetInfo*!");
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RecordVal *RV = R->getValue(Val->getValue());
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int Shift = ShiftInt->getValue();
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if (RV == 0 || RV->getValue() == 0) {
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// This isn't an error if this is a builtin instruction.
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if (R->getName() != "PHI" &&
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R->getName() != "INLINEASM" &&
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R->getName() != "DBG_LABEL" &&
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R->getName() != "EH_LABEL" &&
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R->getName() != "GC_LABEL" &&
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R->getName() != "DECLARE" &&
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R->getName() != "EXTRACT_SUBREG" &&
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R->getName() != "INSERT_SUBREG" &&
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R->getName() != "IMPLICIT_DEF" &&
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R->getName() != "SUBREG_TO_REG" &&
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R->getName() != "COPY_TO_SUBCLASS")
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throw R->getName() + " doesn't have a field named '" +
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Val->getValue() + "'!";
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return;
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}
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Init *Value = RV->getValue();
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if (BitInit *BI = dynamic_cast<BitInit*>(Value)) {
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if (BI->getValue()) OS << "|(1<<" << Shift << ")";
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return;
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} else if (BitsInit *BI = dynamic_cast<BitsInit*>(Value)) {
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// Convert the Bits to an integer to print...
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Init *I = BI->convertInitializerTo(new IntRecTy());
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if (I)
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if (IntInit *II = dynamic_cast<IntInit*>(I)) {
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if (II->getValue()) {
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if (Shift)
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OS << "|(" << II->getValue() << "<<" << Shift << ")";
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else
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OS << "|" << II->getValue();
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}
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return;
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}
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} else if (IntInit *II = dynamic_cast<IntInit*>(Value)) {
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if (II->getValue()) {
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if (Shift)
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OS << "|(" << II->getValue() << "<<" << Shift << ")";
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else
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OS << II->getValue();
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}
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return;
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}
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std::cerr << "Unhandled initializer: " << *Val << "\n";
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throw "In record '" + R->getName() + "' for TSFlag emission.";
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}
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