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https://github.com/c64scene-ar/llvm-6502.git
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5d6365c80c
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.2 KiB
LLVM
37 lines
1.2 KiB
LLVM
; RUN: llc -O0 -fast-isel-abort -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
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@fn.table = internal global [2 x i8*] [i8* blockaddress(@fn, %ZERO), i8* blockaddress(@fn, %ONE)], align 8
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define i32 @fn(i32 %target) nounwind {
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entry:
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; CHECK-LABEL: fn
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%retval = alloca i32, align 4
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%target.addr = alloca i32, align 4
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store i32 %target, i32* %target.addr, align 4
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%0 = load i32* %target.addr, align 4
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%idxprom = zext i32 %0 to i64
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%arrayidx = getelementptr inbounds [2 x i8*]* @fn.table, i32 0, i64 %idxprom
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%1 = load i8** %arrayidx, align 8
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br label %indirectgoto
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ZERO: ; preds = %indirectgoto
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; CHECK: LBB0_1
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store i32 0, i32* %retval
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br label %return
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ONE: ; preds = %indirectgoto
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; CHECK: LBB0_2
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store i32 1, i32* %retval
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br label %return
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return: ; preds = %ONE, %ZERO
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%2 = load i32* %retval
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ret i32 %2
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indirectgoto: ; preds = %entry
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; CHECK: ldr [[REG:x[0-9]+]], [sp]
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; CHECK-NEXT: br [[REG]]
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%indirect.goto.dest = phi i8* [ %1, %entry ]
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indirectbr i8* %indirect.goto.dest, [label %ZERO, label %ONE]
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}
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