mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
239 lines
6.9 KiB
LLVM
239 lines
6.9 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}sdiv24_i8:
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; SI: v_cvt_f32_i32
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; SI: v_cvt_f32_i32
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; SI: v_rcp_f32
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; SI: v_cvt_i32_f32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @sdiv24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
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%num = load i8 addrspace(1) * %in
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%den = load i8 addrspace(1) * %den_ptr
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%result = sdiv i8 %num, %den
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store i8 %result, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}sdiv24_i16:
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; SI: v_cvt_f32_i32
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; SI: v_cvt_f32_i32
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; SI: v_rcp_f32
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; SI: v_cvt_i32_f32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @sdiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
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%num = load i16 addrspace(1) * %in, align 2
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%den = load i16 addrspace(1) * %den_ptr, align 2
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%result = sdiv i16 %num, %den
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store i16 %result, i16 addrspace(1)* %out, align 2
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ret void
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}
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; FUNC-LABEL: {{^}}sdiv24_i32:
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; SI: v_cvt_f32_i32
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; SI: v_cvt_f32_i32
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; SI: v_rcp_f32
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; SI: v_cvt_i32_f32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @sdiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = ashr i32 %num.i24.0, 8
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%den.i24 = ashr i32 %den.i24.0, 8
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%result = sdiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}sdiv25_i32:
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; SI-NOT: v_cvt_f32_i32
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; SI-NOT: v_rcp_f32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @sdiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = ashr i32 %num.i24.0, 7
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%den.i24 = ashr i32 %den.i24.0, 7
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%result = sdiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}test_no_sdiv24_i32_1:
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; SI-NOT: v_cvt_f32_i32
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; SI-NOT: v_rcp_f32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_sdiv24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = ashr i32 %num.i24.0, 8
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%den.i24 = ashr i32 %den.i24.0, 7
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%result = sdiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}test_no_sdiv24_i32_2:
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; SI-NOT: v_cvt_f32_i32
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; SI-NOT: v_rcp_f32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_sdiv24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = ashr i32 %num.i24.0, 7
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%den.i24 = ashr i32 %den.i24.0, 8
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%result = sdiv i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}srem24_i8:
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; SI: v_cvt_f32_i32
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; SI: v_cvt_f32_i32
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; SI: v_rcp_f32
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; SI: v_cvt_i32_f32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @srem24_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) {
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%den_ptr = getelementptr i8 addrspace(1)* %in, i8 1
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%num = load i8 addrspace(1) * %in
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%den = load i8 addrspace(1) * %den_ptr
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%result = srem i8 %num, %den
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store i8 %result, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}srem24_i16:
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; SI: v_cvt_f32_i32
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; SI: v_cvt_f32_i32
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; SI: v_rcp_f32
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; SI: v_cvt_i32_f32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @srem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) {
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%den_ptr = getelementptr i16 addrspace(1)* %in, i16 1
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%num = load i16 addrspace(1) * %in, align 2
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%den = load i16 addrspace(1) * %den_ptr, align 2
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%result = srem i16 %num, %den
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store i16 %result, i16 addrspace(1)* %out, align 2
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ret void
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}
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; FUNC-LABEL: {{^}}srem24_i32:
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; SI: v_cvt_f32_i32
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; SI: v_cvt_f32_i32
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; SI: v_rcp_f32
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; SI: v_cvt_i32_f32
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; EG: INT_TO_FLT
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; EG-DAG: INT_TO_FLT
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; EG-DAG: RECIP_IEEE
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; EG: FLT_TO_INT
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define void @srem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = ashr i32 %num.i24.0, 8
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%den.i24 = ashr i32 %den.i24.0, 8
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%result = srem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}srem25_i32:
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; SI-NOT: v_cvt_f32_i32
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; SI-NOT: v_rcp_f32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @srem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = ashr i32 %num.i24.0, 7
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%den.i24 = ashr i32 %den.i24.0, 7
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%result = srem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}test_no_srem24_i32_1:
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; SI-NOT: v_cvt_f32_i32
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; SI-NOT: v_rcp_f32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_srem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 8
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%den.i24.0 = shl i32 %den, 7
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%num.i24 = ashr i32 %num.i24.0, 8
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%den.i24 = ashr i32 %den.i24.0, 7
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%result = srem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}test_no_srem24_i32_2:
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; SI-NOT: v_cvt_f32_i32
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; SI-NOT: v_rcp_f32
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; EG-NOT: INT_TO_FLT
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; EG-NOT: RECIP_IEEE
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define void @test_no_srem24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%den_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%num = load i32 addrspace(1) * %in, align 4
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%den = load i32 addrspace(1) * %den_ptr, align 4
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%num.i24.0 = shl i32 %num, 7
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%den.i24.0 = shl i32 %den, 8
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%num.i24 = ashr i32 %num.i24.0, 7
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%den.i24 = ashr i32 %den.i24.0, 8
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%result = srem i32 %num.i24, %den.i24
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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