llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-17 03:30:28 +00:00

History

Chris Lattner 26d4fdb968 Fix a minor bug (ORo didn't mark that it set CR0). Refactor how . instructions are handled. In particular, instead of passing the RC flag all the way up the inheritance hierarchy, just make a new tblgen class 'DOT' which can be added to an instruction definition. For example, instead of this: -def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), -let Defs = [CR0] in -def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), - "and. $rA, $rS, $rB">; We now have this: +def AND : XForm_6<31, 28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), "and $rA, $rS, $rB">; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21225 91177308-0d34-0410-b5e6-96231b3b80d8		2005-04-11 15:01:39 +00:00
..
.cvsignore
LICENSE.TXT
Makefile	Specify all of the targets built.	2004-12-16 17:26:44 +00:00
PowerPC.td
PowerPCInstrInfo.h
PowerPCTargetMachine.h
PPC32.td
PPC32ISelSimple.cpp	rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more	2005-04-10 01:03:31 +00:00
PPC32JITInfo.h
PPC32RegisterInfo.td
PPC64.td
PPC64CodeEmitter.cpp
PPC64InstrInfo.cpp
PPC64InstrInfo.h
PPC64ISelPattern.cpp	This target does not yet support ISD::BRCONDTWOWAY	2005-04-09 03:22:30 +00:00
PPC64JITInfo.h
PPC64RegisterInfo.cpp
PPC64RegisterInfo.h
PPC64RegisterInfo.td
PPC64TargetMachine.h
PPC.h	Remove 64 bit simple ISel, it never worked correctly	2005-04-05 08:51:15 +00:00
PPCAsmPrinter.cpp	Make sure that BRCOND branches can be converted into long branches too.	2005-04-10 01:48:29 +00:00
PPCBranchSelector.cpp
PPCCodeEmitter.cpp
PPCFrameInfo.h
PPCInstrBuilder.h
PPCInstrFormats.td	Fix a minor bug (ORo didn't mark that it set CR0).	2005-04-11 15:01:39 +00:00
PPCInstrInfo.cpp
PPCInstrInfo.h
PPCInstrInfo.td	Fix a minor bug (ORo didn't mark that it set CR0).	2005-04-11 15:01:39 +00:00
PPCISelPattern.cpp	Add recording variants of ISD::AND and ISD::OR. This kills almost 1000	2005-04-11 06:34:10 +00:00
PPCJITInfo.cpp
PPCJITInfo.h
PPCRegisterInfo.cpp	Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not	2005-04-10 03:59:42 +00:00
PPCRegisterInfo.h
PPCRegisterInfo.td
PPCRelocations.h
PPCTargetMachine.cpp	Remove 64 bit simple ISel, it never worked correctly	2005-04-05 08:51:15 +00:00
PPCTargetMachine.h
README.txt

README.txt

TODO:
* poor switch statement codegen
* load/store to alloca'd array or struct.
* implement not-R0 register GPR class
* implement scheduling info
* implement do-loop pass
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* implement powerpc-64 for aix
* use stfiwx in float->int
* should hint to the branch select pass that it doesn't need to print the
  second unconditional branch, so we don't end up with things like:
	b .LBBl42__2E_expand_function_8_674	; loopentry.24
	b .LBBl42__2E_expand_function_8_42	; NewDefault
	b .LBBl42__2E_expand_function_8_42	; NewDefault

Currently failing tests that should pass:
* MultiSource
  |- Applications
  |  `- hbd: miscompilation