llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-04 06:09:05 +00:00

History

Chris Lattner 7c306da505 Sink InstructionSelect() out of each target into SDISel, and rename it DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader. Sink some other stuff out of DAGISelHeader into SDISel. Eliminate the various 'Indent' stuff from various targets, which dates to when isel was recursive. 17 files changed, 114 insertions(+), 430 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8		2010-03-02 06:34:30 +00:00
..
AsmPrinter	"Fix and issue in SparcAsmPrinter where multiple identical .LLGETPCHn symbols could be emitted in the same file (it was uniqued by block number, but not by function number). " Patch by Nathan Keynes!	2010-02-17 18:57:19 +00:00
TargetInfo	add support for the sparcv9-- target triple to turn on	2010-02-04 06:34:01 +00:00
CMakeLists.txt
DelaySlotFiller.cpp
FPMover.cpp
Makefile	make -fno-rtti the default unless a directory builds with REQUIRES_RTTI.	2010-01-24 20:43:08 +00:00
README.txt	Add JIT support to the TODO list (test commit)	2010-03-01 10:40:41 +00:00
Sparc.h	add support for the sparcv9-- target triple to turn on	2010-02-04 06:34:01 +00:00
Sparc.td
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td
SparcISelDAGToDAG.cpp	Sink InstructionSelect() out of each target into SDISel, and rename it	2010-03-02 06:34:30 +00:00
SparcISelLowering.cpp	Move TLOF implementations to libCodegen to resolve layering violation.	2010-02-15 22:37:53 +00:00
SparcISelLowering.h	Revert 95130.	2010-02-02 23:55:14 +00:00
SparcMachineFunctionInfo.h	Add explicit keywords.	2010-03-01 17:56:46 +00:00
SparcMCAsmInfo.cpp	Eliminate SetDirective, and replace it with HasSetDirective.	2010-01-26 20:40:54 +00:00
SparcMCAsmInfo.h
SparcRegisterInfo.cpp
SparcRegisterInfo.h
SparcRegisterInfo.td
SparcSubtarget.cpp	add support for the sparcv9-- target triple to turn on	2010-02-04 06:34:01 +00:00
SparcSubtarget.h	add support for the sparcv9-- target triple to turn on	2010-02-04 06:34:01 +00:00
SparcTargetMachine.cpp	add support for the sparcv9-- target triple to turn on	2010-02-04 06:34:01 +00:00
SparcTargetMachine.h	add support for the sparcv9-- target triple to turn on	2010-02-04 06:34:01 +00:00

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support