mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-30 04:56:49 +00:00
538287dea2
The ABI allows sub-128 vectors to be passed and returned in registers, with the vector occupying the upper part of a register. We therefore want to legalize those types by widening the vector rather than promoting the elements. The patch includes some simple tests for sub-128 vectors and also tests that we can recognize various pack sequences, some of which use sub-128 vectors as temporary results. One of these forms is based on the pack sequences generated by llvmpipe when no intrinsics are used. Signed unpacks are recognized as BUILD_VECTORs whose elements are individually sign-extended. Unsigned unpacks can have the equivalent form with zero extension, but they also occur as shuffles in which some elements are zero. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236525 91177308-0d34-0410-b5e6-96231b3b80d8
33 lines
1.1 KiB
LLVM
33 lines
1.1 KiB
LLVM
; Test the handling of unnamed short vector arguments.
|
|
;
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-STACK
|
|
|
|
; This routine is called with two named vector argument (passed
|
|
; in %v24 and %v26) and two unnamed vector arguments (passed
|
|
; in the single-wide stack slots at 160 and 168).
|
|
declare void @bar(<4 x i8>, <4 x i8>, ...)
|
|
|
|
define void @foo() {
|
|
; CHECK-VEC-LABEL: foo:
|
|
; CHECK-VEC-DAG: vrepib %v24, 1
|
|
; CHECK-VEC-DAG: vrepib %v26, 2
|
|
; CHECK-VEC: brasl %r14, bar@PLT
|
|
;
|
|
; CHECK-STACK-LABEL: foo:
|
|
; CHECK-STACK: aghi %r15, -176
|
|
; CHECK-STACK-DAG: llihf [[REG1:%r[0-9]+]], 50529027
|
|
; CHECK-STACK-DAG: stg [[REG1]], 160(%r15)
|
|
; CHECK-STACK-DAG: llihf [[REG2:%r[0-9]+]], 67372036
|
|
; CHECK-STACK-DAG: stg [[REG2]], 168(%r15)
|
|
; CHECK-STACK: brasl %r14, bar@PLT
|
|
|
|
call void (<4 x i8>, <4 x i8>, ...) @bar
|
|
(<4 x i8> <i8 1, i8 1, i8 1, i8 1>,
|
|
<4 x i8> <i8 2, i8 2, i8 2, i8 2>,
|
|
<4 x i8> <i8 3, i8 3, i8 3, i8 3>,
|
|
<4 x i8> <i8 4, i8 4, i8 4, i8 4>)
|
|
ret void
|
|
}
|
|
|