mirror of
https://github.com/c64scene-ar/llvm-6502.git
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86a791284a
The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
4.4 KiB
TableGen
98 lines
4.4 KiB
TableGen
//======--- SPUMathInst.td - Cell SPU math operations -*- tablegen -*---======//
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//
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// Cell SPU math operations
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//
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// This target description file contains instruction sequences for various
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// math operations, such as vector multiplies, i32 multiply, etc., for the
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// SPU's i32, i16 i8 and corresponding vector types.
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//
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// Any resemblance to libsimdmath or the Cell SDK simdmath library is
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// purely and completely coincidental.
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//===----------------------------------------------------------------------===//
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// v16i8 multiply instruction sequence:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def : Pat<(mul (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)),
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(ORv4i32
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(ANDv4i32
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(SELBv4i32 (MPYv8i16 VECREG:$rA, VECREG:$rB),
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(SHLHIv8i16 (MPYv8i16 (ROTMAHIv8i16 VECREG:$rA, 8),
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(ROTMAHIv8i16 VECREG:$rB, 8)), 8),
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(FSMBIv8i16 0x2222)),
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(ILAv4i32 0x0000ffff)),
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(SHLIv4i32
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(SELBv4i32 (MPYv8i16 (ROTMAIv4i32_i32 VECREG:$rA, 16),
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(ROTMAIv4i32_i32 VECREG:$rB, 16)),
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(SHLHIv8i16 (MPYv8i16 (ROTMAIv4i32_i32 VECREG:$rA, 8),
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(ROTMAIv4i32_i32 VECREG:$rB, 8)), 8),
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(FSMBIv8i16 0x2222)), 16))>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// v8i16 multiply instruction sequence:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def : Pat<(mul (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)),
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(SELBv8i16 (MPYv8i16 VECREG:$rA, VECREG:$rB),
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(SHLIv4i32 (MPYHHv8i16 VECREG:$rA, VECREG:$rB), 16),
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(FSMBIv8i16 0xcccc))>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// v4i32, i32 multiply instruction sequence:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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def MPYv4i32:
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Pat<(mul (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
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(Av4i32
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(v4i32 (Av4i32 (v4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB)),
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(v4i32 (MPYHv4i32 VECREG:$rB, VECREG:$rA)))),
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(v4i32 (MPYUv4i32 VECREG:$rA, VECREG:$rB)))>;
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def MPYi32:
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Pat<(mul R32C:$rA, R32C:$rB),
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(Ar32
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(Ar32 (MPYHr32 R32C:$rA, R32C:$rB),
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(MPYHr32 R32C:$rB, R32C:$rA)),
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(MPYUr32 R32C:$rA, R32C:$rB))>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// f32, v4f32 divide instruction sequence:
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// Reciprocal estimate and interpolation
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def Interpf32: CodeFrag<(FIf32 R32FP:$rB, (FRESTf32 R32FP:$rB))>;
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// Division estimate
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def DivEstf32: CodeFrag<(FMf32 R32FP:$rA, Interpf32.Fragment)>;
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// Newton-Raphson iteration
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def NRaphf32: CodeFrag<(FMAf32 (FNMSf32 DivEstf32.Fragment, R32FP:$rB, R32FP:$rA),
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Interpf32.Fragment,
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DivEstf32.Fragment)>;
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// Epsilon addition
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def Epsilonf32: CodeFrag<(AIf32 NRaphf32.Fragment, 1)>;
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def : Pat<(fdiv R32FP:$rA, R32FP:$rB),
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(SELBf32_cond NRaphf32.Fragment,
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Epsilonf32.Fragment,
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(CGTIf32 (FNMSf32 R32FP:$rB, Epsilonf32.Fragment, R32FP:$rA), -1))>;
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// Reciprocal estimate and interpolation
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def Interpv4f32: CodeFrag<(FIv4f32 (v4f32 VECREG:$rB), (FRESTv4f32 (v4f32 VECREG:$rB)))>;
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// Division estimate
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def DivEstv4f32: CodeFrag<(FMv4f32 (v4f32 VECREG:$rA), Interpv4f32.Fragment)>;
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// Newton-Raphson iteration
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def NRaphv4f32: CodeFrag<(FMAv4f32 (FNMSv4f32 DivEstv4f32.Fragment,
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(v4f32 VECREG:$rB),
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(v4f32 VECREG:$rA)),
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Interpv4f32.Fragment,
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DivEstv4f32.Fragment)>;
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// Epsilon addition
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def Epsilonv4f32: CodeFrag<(AIv4f32 NRaphv4f32.Fragment, 1)>;
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def : Pat<(fdiv (v4f32 VECREG:$rA), (v4f32 VECREG:$rB)),
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(SELBv4f32_cond NRaphv4f32.Fragment,
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Epsilonv4f32.Fragment,
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(CGTIv4f32 (FNMSv4f32 (v4f32 VECREG:$rB),
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Epsilonv4f32.Fragment,
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(v4f32 VECREG:$rA)), -1))>;
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