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https://github.com/c64scene-ar/llvm-6502.git
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c50e2bcdf7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30946 91177308-0d34-0410-b5e6-96231b3b80d8
258 lines
8.6 KiB
C++
258 lines
8.6 KiB
C++
//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCInstrInfo.h"
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#include "PPCGenInstrInfo.inc"
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#include "PPCTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include <iostream>
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using namespace llvm;
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PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
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: TargetInstrInfo(PPCInsts, sizeof(PPCInsts)/sizeof(PPCInsts[0])), TM(tm),
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RI(*TM.getSubtargetImpl()) {}
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/// getPointerRegClass - Return the register class to use to hold pointers.
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/// This is used for addressing modes.
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const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
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if (TM.getSubtargetImpl()->isPPC64())
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return &PPC::G8RCRegClass;
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else
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return &PPC::GPRCRegClass;
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}
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bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
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oc == PPC::OR4To8 || oc == PPC::OR8To4) { // or r1, r2, r2
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isRegister() &&
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"invalid PPC OR instruction!");
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if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::ADDI) { // addi r1, r2, 0
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(2).isImmediate() &&
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"invalid PPC ADDI instruction!");
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if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::ORI) { // ori r1, r2, 0
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isImmediate() &&
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"invalid PPC ORI instruction!");
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if (MI.getOperand(2).getImmedValue()==0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::FMRS || oc == PPC::FMRD ||
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oc == PPC::FMRSD) { // fmr r1, r2
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid PPC FMR instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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} else if (oc == PPC::MCRF) { // mcrf cr1, cr2
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid PPC MCRF instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case PPC::LD:
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case PPC::LWZ:
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case PPC::LFS:
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case PPC::LFD:
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if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
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MI->getOperand(2).isFrameIndex()) {
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FrameIndex = MI->getOperand(2).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case PPC::STD:
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case PPC::STW:
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case PPC::STFS:
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case PPC::STFD:
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if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
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MI->getOperand(2).isFrameIndex()) {
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FrameIndex = MI->getOperand(2).getFrameIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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// commuteInstruction - We can commute rlwimi instructions, but only if the
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// rotate amt is zero. We also have to munge the immediates a bit.
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MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
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// Normal instructions can be commuted the obvious way.
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if (MI->getOpcode() != PPC::RLWIMI)
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return TargetInstrInfo::commuteInstruction(MI);
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// Cannot commute if it has a non-zero rotate count.
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if (MI->getOperand(3).getImmedValue() != 0)
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return 0;
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// If we have a zero rotate count, we have:
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// M = mask(MB,ME)
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// Op0 = (Op1 & ~M) | (Op2 & M)
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// Change this to:
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// M = mask((ME+1)&31, (MB-1)&31)
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// Op0 = (Op2 & ~M) | (Op1 & M)
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// Swap op1/op2
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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// Swap the mask around.
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unsigned MB = MI->getOperand(4).getImmedValue();
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unsigned ME = MI->getOperand(5).getImmedValue();
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MI->getOperand(4).setImmedValue((ME+1) & 31);
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MI->getOperand(5).setImmedValue((MB-1) & 31);
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return MI;
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}
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void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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BuildMI(MBB, MI, PPC::NOP, 0);
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}
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// Branch analysis.
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bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode()))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
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if (LastInst->getOpcode() == PPC::B) {
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TBB = LastInst->getOperand(0).getMachineBasicBlock();
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return false;
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} else if (LastInst->getOpcode() == PPC::COND_BRANCH) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(2).getMachineBasicBlock();
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Cond.push_back(LastInst->getOperand(0));
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Cond.push_back(LastInst->getOperand(1));
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return true;
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}
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// Otherwise, don't know what this is.
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return true;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() &&
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isTerminatorInstr((--I)->getOpcode()))
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return true;
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// If the block ends with PPC::B and PPC:COND_BRANCH, handle it.
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if (SecondLastInst->getOpcode() == PPC::COND_BRANCH &&
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LastInst->getOpcode() == PPC::B) {
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TBB = SecondLastInst->getOperand(2).getMachineBasicBlock();
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Cond.push_back(SecondLastInst->getOperand(0));
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Cond.push_back(SecondLastInst->getOperand(1));
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FBB = LastInst->getOperand(0).getMachineBasicBlock();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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void PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return;
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--I;
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if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::COND_BRANCH)
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return;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return;
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--I;
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if (I->getOpcode() != PPC::COND_BRANCH)
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return;
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// Remove the branch.
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I->eraseFromParent();
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}
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void PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond) const {
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// Fall through?
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if (TBB == 0 && FBB == 0) return;
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assert(Cond.size() == 2 && "PPC branch conditions have two components!");
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// Conditional branch
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BuildMI(&MBB, PPC::COND_BRANCH, 3)
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.addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
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if (FBB) // Two-way branch.
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BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
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}
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bool PPCInstrInfo::
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ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
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return true;
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}
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