mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242916 91177308-0d34-0410-b5e6-96231b3b80d8
494 lines
17 KiB
C++
494 lines
17 KiB
C++
//===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the class that prints out the LLVM IR and machine
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// functions using the MIR serialization format.
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//
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//===----------------------------------------------------------------------===//
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#include "MIRPrinter.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IRPrintingPasses.h"
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#include "llvm/IR/Module.h"
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#include "llvm/IR/ModuleSlotTracker.h"
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#include "llvm/Support/MemoryBuffer.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Support/YAMLTraits.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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namespace {
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/// This structure describes how to print out stack object references.
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struct FrameIndexOperand {
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std::string Name;
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unsigned ID;
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bool IsFixed;
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FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
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: Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
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/// Return an ordinary stack object reference.
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static FrameIndexOperand create(StringRef Name, unsigned ID) {
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return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
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}
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/// Return a fixed stack object reference.
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static FrameIndexOperand createFixed(unsigned ID) {
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return FrameIndexOperand("", ID, /*IsFixed=*/true);
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}
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};
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/// This class prints out the machine functions using the MIR serialization
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/// format.
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class MIRPrinter {
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raw_ostream &OS;
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DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
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/// Maps from stack object indices to operand indices which will be used when
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/// printing frame index machine operands.
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DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
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public:
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MIRPrinter(raw_ostream &OS) : OS(OS) {}
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void print(const MachineFunction &MF);
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void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI);
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void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
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void convert(yaml::MachineFunction &MF,
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const MachineConstantPool &ConstantPool);
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void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
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const MachineJumpTableInfo &JTI);
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void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
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const MachineBasicBlock &MBB);
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void convertStackObjects(yaml::MachineFunction &MF,
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const MachineFrameInfo &MFI);
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private:
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void initRegisterMaskIds(const MachineFunction &MF);
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};
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/// This class prints out the machine instructions using the MIR serialization
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/// format.
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class MIPrinter {
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raw_ostream &OS;
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ModuleSlotTracker &MST;
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
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const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
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public:
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MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
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const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
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const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
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: OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
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StackObjectOperandMapping(StackObjectOperandMapping) {}
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void print(const MachineInstr &MI);
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void printMBBReference(const MachineBasicBlock &MBB);
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void printStackObjectReference(int FrameIndex);
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void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
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void print(const MCCFIInstruction &CFI);
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};
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} // end anonymous namespace
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namespace llvm {
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namespace yaml {
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/// This struct serializes the LLVM IR module.
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template <> struct BlockScalarTraits<Module> {
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static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
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Mod.print(OS, nullptr);
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}
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static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
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llvm_unreachable("LLVM Module is supposed to be parsed separately");
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return "";
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}
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};
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} // end namespace yaml
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} // end namespace llvm
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static void printReg(unsigned Reg, raw_ostream &OS,
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const TargetRegisterInfo *TRI) {
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// TODO: Print Stack Slots.
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if (!Reg)
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OS << '_';
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else if (TargetRegisterInfo::isVirtualRegister(Reg))
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OS << '%' << TargetRegisterInfo::virtReg2Index(Reg);
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else if (Reg < TRI->getNumRegs())
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OS << '%' << StringRef(TRI->getName(Reg)).lower();
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else
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llvm_unreachable("Can't print this kind of register yet");
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}
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void MIRPrinter::print(const MachineFunction &MF) {
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initRegisterMaskIds(MF);
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yaml::MachineFunction YamlMF;
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YamlMF.Name = MF.getName();
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YamlMF.Alignment = MF.getAlignment();
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YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
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YamlMF.HasInlineAsm = MF.hasInlineAsm();
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convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
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convert(YamlMF.FrameInfo, *MF.getFrameInfo());
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convertStackObjects(YamlMF, *MF.getFrameInfo());
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if (const auto *ConstantPool = MF.getConstantPool())
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convert(YamlMF, *ConstantPool);
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ModuleSlotTracker MST(MF.getFunction()->getParent());
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if (const auto *JumpTableInfo = MF.getJumpTableInfo())
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convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
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int I = 0;
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for (const auto &MBB : MF) {
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// TODO: Allow printing of non sequentially numbered MBBs.
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// This is currently needed as the basic block references get their index
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// from MBB.getNumber(), thus it should be sequential so that the parser can
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// map back to the correct MBBs when parsing the output.
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assert(MBB.getNumber() == I++ &&
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"Can't print MBBs that aren't sequentially numbered");
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(void)I;
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yaml::MachineBasicBlock YamlMBB;
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convert(MST, YamlMBB, MBB);
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YamlMF.BasicBlocks.push_back(YamlMBB);
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}
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yaml::Output Out(OS);
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Out << YamlMF;
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}
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void MIRPrinter::convert(yaml::MachineFunction &MF,
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const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI) {
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MF.IsSSA = RegInfo.isSSA();
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MF.TracksRegLiveness = RegInfo.tracksLiveness();
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MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
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// Print the virtual register definitions.
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for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
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yaml::VirtualRegisterDefinition VReg;
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VReg.ID = I;
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VReg.Class =
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StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
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MF.VirtualRegisters.push_back(VReg);
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}
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}
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void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
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const MachineFrameInfo &MFI) {
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YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
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YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
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YamlMFI.HasStackMap = MFI.hasStackMap();
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YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
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YamlMFI.StackSize = MFI.getStackSize();
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YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
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YamlMFI.MaxAlignment = MFI.getMaxAlignment();
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YamlMFI.AdjustsStack = MFI.adjustsStack();
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YamlMFI.HasCalls = MFI.hasCalls();
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YamlMFI.MaxCallFrameSize = MFI.getMaxCallFrameSize();
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YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
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YamlMFI.HasVAStart = MFI.hasVAStart();
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YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
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}
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void MIRPrinter::convertStackObjects(yaml::MachineFunction &MF,
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const MachineFrameInfo &MFI) {
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// Process fixed stack objects.
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unsigned ID = 0;
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for (int I = MFI.getObjectIndexBegin(); I < 0; ++I) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::FixedMachineStackObject YamlObject;
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YamlObject.ID = ID;
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::FixedMachineStackObject::SpillSlot
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: yaml::FixedMachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
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YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
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MF.FixedStackObjects.push_back(YamlObject);
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StackObjectOperandMapping.insert(
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std::make_pair(I, FrameIndexOperand::createFixed(ID++)));
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}
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// Process ordinary stack objects.
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ID = 0;
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for (int I = 0, E = MFI.getObjectIndexEnd(); I < E; ++I) {
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if (MFI.isDeadObjectIndex(I))
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continue;
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yaml::MachineStackObject YamlObject;
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YamlObject.ID = ID;
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if (const auto *Alloca = MFI.getObjectAllocation(I))
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YamlObject.Name.Value =
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Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>";
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YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
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? yaml::MachineStackObject::SpillSlot
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: MFI.isVariableSizedObjectIndex(I)
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? yaml::MachineStackObject::VariableSized
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: yaml::MachineStackObject::DefaultType;
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YamlObject.Offset = MFI.getObjectOffset(I);
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YamlObject.Size = MFI.getObjectSize(I);
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YamlObject.Alignment = MFI.getObjectAlignment(I);
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MF.StackObjects.push_back(YamlObject);
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StackObjectOperandMapping.insert(std::make_pair(
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I, FrameIndexOperand::create(YamlObject.Name.Value, ID++)));
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}
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}
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void MIRPrinter::convert(yaml::MachineFunction &MF,
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const MachineConstantPool &ConstantPool) {
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unsigned ID = 0;
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for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
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// TODO: Serialize target specific constant pool entries.
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if (Constant.isMachineConstantPoolEntry())
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llvm_unreachable("Can't print target specific constant pool entries yet");
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yaml::MachineConstantPoolValue YamlConstant;
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std::string Str;
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raw_string_ostream StrOS(Str);
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Constant.Val.ConstVal->printAsOperand(StrOS);
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YamlConstant.ID = ID++;
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YamlConstant.Value = StrOS.str();
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YamlConstant.Alignment = Constant.getAlignment();
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MF.Constants.push_back(YamlConstant);
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}
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}
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void MIRPrinter::convert(ModuleSlotTracker &MST,
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yaml::MachineJumpTable &YamlJTI,
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const MachineJumpTableInfo &JTI) {
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YamlJTI.Kind = JTI.getEntryKind();
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unsigned ID = 0;
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for (const auto &Table : JTI.getJumpTables()) {
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std::string Str;
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yaml::MachineJumpTable::Entry Entry;
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Entry.ID = ID++;
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for (const auto *MBB : Table.MBBs) {
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raw_string_ostream StrOS(Str);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.printMBBReference(*MBB);
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Entry.Blocks.push_back(StrOS.str());
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Str.clear();
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}
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YamlJTI.Entries.push_back(Entry);
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}
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}
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void MIRPrinter::convert(ModuleSlotTracker &MST,
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yaml::MachineBasicBlock &YamlMBB,
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const MachineBasicBlock &MBB) {
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assert(MBB.getNumber() >= 0 && "Invalid MBB number");
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YamlMBB.ID = (unsigned)MBB.getNumber();
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// TODO: Serialize unnamed BB references.
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if (const auto *BB = MBB.getBasicBlock())
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YamlMBB.Name.Value = BB->hasName() ? BB->getName() : "<unnamed bb>";
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else
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YamlMBB.Name.Value = "";
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YamlMBB.Alignment = MBB.getAlignment();
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YamlMBB.AddressTaken = MBB.hasAddressTaken();
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YamlMBB.IsLandingPad = MBB.isLandingPad();
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for (const auto *SuccMBB : MBB.successors()) {
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std::string Str;
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raw_string_ostream StrOS(Str);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
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.printMBBReference(*SuccMBB);
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YamlMBB.Successors.push_back(StrOS.str());
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}
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// Print the live in registers.
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const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
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assert(TRI && "Expected target register info");
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for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
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std::string Str;
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raw_string_ostream StrOS(Str);
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printReg(*I, StrOS, TRI);
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YamlMBB.LiveIns.push_back(StrOS.str());
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}
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// Print the machine instructions.
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YamlMBB.Instructions.reserve(MBB.size());
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std::string Str;
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for (const auto &MI : MBB) {
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raw_string_ostream StrOS(Str);
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MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping).print(MI);
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YamlMBB.Instructions.push_back(StrOS.str());
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Str.clear();
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}
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}
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void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
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const auto *TRI = MF.getSubtarget().getRegisterInfo();
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unsigned I = 0;
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for (const uint32_t *Mask : TRI->getRegMasks())
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RegisterMaskIds.insert(std::make_pair(Mask, I++));
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}
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void MIPrinter::print(const MachineInstr &MI) {
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const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
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const auto *TRI = SubTarget.getRegisterInfo();
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assert(TRI && "Expected target register info");
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const auto *TII = SubTarget.getInstrInfo();
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assert(TII && "Expected target instruction info");
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if (MI.isCFIInstruction())
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assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
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unsigned I = 0, E = MI.getNumOperands();
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for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
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!MI.getOperand(I).isImplicit();
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++I) {
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if (I)
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OS << ", ";
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print(MI.getOperand(I), TRI);
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}
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if (I)
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OS << " = ";
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if (MI.getFlag(MachineInstr::FrameSetup))
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OS << "frame-setup ";
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OS << TII->getName(MI.getOpcode());
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// TODO: Print the bundling instruction flags, machine mem operands.
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if (I < E)
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OS << ' ';
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bool NeedComma = false;
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for (; I < E; ++I) {
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if (NeedComma)
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OS << ", ";
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print(MI.getOperand(I), TRI);
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NeedComma = true;
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}
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}
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void MIPrinter::printMBBReference(const MachineBasicBlock &MBB) {
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OS << "%bb." << MBB.getNumber();
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if (const auto *BB = MBB.getBasicBlock()) {
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if (BB->hasName())
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OS << '.' << BB->getName();
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}
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}
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void MIPrinter::printStackObjectReference(int FrameIndex) {
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auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
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assert(ObjectInfo != StackObjectOperandMapping.end() &&
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"Invalid frame index");
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const FrameIndexOperand &Operand = ObjectInfo->second;
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if (Operand.IsFixed) {
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OS << "%fixed-stack." << Operand.ID;
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return;
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}
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OS << "%stack." << Operand.ID;
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if (!Operand.Name.empty())
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OS << '.' << Operand.Name;
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}
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void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
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switch (Op.getType()) {
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case MachineOperand::MO_Register:
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// TODO: Print the other register flags.
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if (Op.isImplicit())
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OS << (Op.isDef() ? "implicit-def " : "implicit ");
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if (Op.isDead())
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OS << "dead ";
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if (Op.isKill())
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OS << "killed ";
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if (Op.isUndef())
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OS << "undef ";
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printReg(Op.getReg(), OS, TRI);
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// Print the sub register.
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if (Op.getSubReg() != 0)
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OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
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break;
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case MachineOperand::MO_Immediate:
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OS << Op.getImm();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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printMBBReference(*Op.getMBB());
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break;
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case MachineOperand::MO_FrameIndex:
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printStackObjectReference(Op.getIndex());
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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OS << "%const." << Op.getIndex();
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// TODO: Print offset and target flags.
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break;
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case MachineOperand::MO_JumpTableIndex:
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OS << "%jump-table." << Op.getIndex();
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// TODO: Print target flags.
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << '$';
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printLLVMNameWithoutPrefix(OS, Op.getSymbolName());
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// TODO: Print the target flags.
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break;
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case MachineOperand::MO_GlobalAddress:
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Op.getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
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// TODO: Print offset and target flags.
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break;
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case MachineOperand::MO_RegisterMask: {
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auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
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if (RegMaskInfo != RegisterMaskIds.end())
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OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
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else
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llvm_unreachable("Can't print this machine register mask yet.");
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break;
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}
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case MachineOperand::MO_Metadata:
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Op.getMetadata()->printAsOperand(OS, MST);
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break;
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case MachineOperand::MO_CFIIndex: {
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const auto &MMI = Op.getParent()->getParent()->getParent()->getMMI();
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print(MMI.getFrameInstructions()[Op.getCFIIndex()]);
|
|
break;
|
|
}
|
|
default:
|
|
// TODO: Print the other machine operands.
|
|
llvm_unreachable("Can't print this machine operand at the moment");
|
|
}
|
|
}
|
|
|
|
void MIPrinter::print(const MCCFIInstruction &CFI) {
|
|
switch (CFI.getOperation()) {
|
|
case MCCFIInstruction::OpDefCfaOffset:
|
|
OS << ".cfi_def_cfa_offset ";
|
|
if (CFI.getLabel())
|
|
OS << "<mcsymbol> ";
|
|
OS << CFI.getOffset();
|
|
break;
|
|
default:
|
|
// TODO: Print the other CFI Operations.
|
|
OS << "<unserializable cfi operation>";
|
|
break;
|
|
}
|
|
}
|
|
|
|
void llvm::printMIR(raw_ostream &OS, const Module &M) {
|
|
yaml::Output Out(OS);
|
|
Out << const_cast<Module &>(M);
|
|
}
|
|
|
|
void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
|
|
MIRPrinter Printer(OS);
|
|
Printer.print(MF);
|
|
}
|