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https://github.com/c64scene-ar/llvm-6502.git
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Spot by Bruno. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241505 91177308-0d34-0410-b5e6-96231b3b80d8
1796 lines
64 KiB
C++
1796 lines
64 KiB
C++
//===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the TwoAddress instruction pass which is used
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// by most register allocators. Two-Address instructions are rewritten
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// from:
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//
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// A = B op C
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//
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// to:
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//
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// A = B
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// A op= C
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//
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// Note that if a register allocator chooses to use this pass, that it
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// has to be capable of handling the non-SSA nature of these rewritten
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// virtual registers.
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//
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// It is also worth noting that the duplicate operand of the two
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// address instruction is removed.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "twoaddrinstr"
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STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
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STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
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STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
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STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
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STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
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STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
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STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
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// Temporary flag to disable rescheduling.
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static cl::opt<bool>
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EnableRescheduling("twoaddr-reschedule",
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cl::desc("Coalesce copies by rescheduling (default=true)"),
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cl::init(true), cl::Hidden);
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namespace {
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class TwoAddressInstructionPass : public MachineFunctionPass {
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const InstrItineraryData *InstrItins;
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MachineRegisterInfo *MRI;
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LiveVariables *LV;
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LiveIntervals *LIS;
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AliasAnalysis *AA;
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CodeGenOpt::Level OptLevel;
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// The current basic block being processed.
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MachineBasicBlock *MBB;
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// DistanceMap - Keep track the distance of a MI from the start of the
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// current basic block.
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DenseMap<MachineInstr*, unsigned> DistanceMap;
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// Set of already processed instructions in the current block.
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SmallPtrSet<MachineInstr*, 8> Processed;
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// SrcRegMap - A map from virtual registers to physical registers which are
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// likely targets to be coalesced to due to copies from physical registers to
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// virtual registers. e.g. v1024 = move r0.
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DenseMap<unsigned, unsigned> SrcRegMap;
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// DstRegMap - A map from virtual registers to physical registers which are
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// likely targets to be coalesced to due to copies to physical registers from
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// virtual registers. e.g. r1 = move v1024.
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DenseMap<unsigned, unsigned> DstRegMap;
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bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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bool isRevCopyChain(unsigned FromReg, unsigned ToReg, int Maxlen);
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bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
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bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
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MachineInstr *MI, unsigned Dist);
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bool commuteInstruction(MachineBasicBlock::iterator &mi,
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unsigned RegB, unsigned RegC, unsigned Dist);
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bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
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bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned RegA, unsigned RegB, unsigned Dist);
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bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
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bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg);
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bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg);
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bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned SrcIdx, unsigned DstIdx,
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unsigned Dist, bool shouldOnlyCommute);
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void scanUses(unsigned DstReg);
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void processCopy(MachineInstr *MI);
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typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
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typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
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bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
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void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
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void eliminateRegSequence(MachineBasicBlock::iterator&);
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public:
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static char ID; // Pass identification, replacement for typeid
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TwoAddressInstructionPass() : MachineFunctionPass(ID) {
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initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<LiveVariables>();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - Pass entry point.
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bool runOnMachineFunction(MachineFunction&) override;
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};
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} // end anonymous namespace
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char TwoAddressInstructionPass::ID = 0;
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INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
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"Two-Address instruction pass", false, false)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
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"Two-Address instruction pass", false, false)
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char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
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static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
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/// sink3AddrInstruction - A two-address instruction has been converted to a
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/// three-address instruction to avoid clobbering a register. Try to sink it
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/// past the instruction that would kill the above mentioned register to reduce
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/// register pressure.
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bool TwoAddressInstructionPass::
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sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
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MachineBasicBlock::iterator OldPos) {
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// FIXME: Shouldn't we be trying to do this before we three-addressify the
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// instruction? After this transformation is done, we no longer need
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// the instruction to be in three-address form.
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// Check if it's safe to move this instruction.
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bool SeenStore = true; // Be conservative.
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if (!MI->isSafeToMove(AA, SeenStore))
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return false;
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unsigned DefReg = 0;
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SmallSet<unsigned, 4> UseRegs;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (MO.isUse() && MOReg != SavedReg)
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UseRegs.insert(MO.getReg());
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if (!MO.isDef())
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continue;
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if (MO.isImplicit())
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// Don't try to move it if it implicitly defines a register.
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return false;
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if (DefReg)
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// For now, don't move any instructions that define multiple registers.
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return false;
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DefReg = MO.getReg();
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}
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// Find the instruction that kills SavedReg.
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MachineInstr *KillMI = nullptr;
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if (LIS) {
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LiveInterval &LI = LIS->getInterval(SavedReg);
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assert(LI.end() != LI.begin() &&
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"Reg should not have empty live interval.");
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SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
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LiveInterval::const_iterator I = LI.find(MBBEndIdx);
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if (I != LI.end() && I->start < MBBEndIdx)
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return false;
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--I;
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KillMI = LIS->getInstructionFromIndex(I->end);
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}
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if (!KillMI) {
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for (MachineRegisterInfo::use_nodbg_iterator
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UI = MRI->use_nodbg_begin(SavedReg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = *UI;
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if (!UseMO.isKill())
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continue;
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KillMI = UseMO.getParent();
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break;
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}
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}
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// If we find the instruction that kills SavedReg, and it is in an
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// appropriate location, we can try to sink the current instruction
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// past it.
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if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
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KillMI == OldPos || KillMI->isTerminator())
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return false;
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// If any of the definitions are used by another instruction between the
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// position and the kill use, then it's not safe to sink it.
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//
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// FIXME: This can be sped up if there is an easy way to query whether an
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// instruction is before or after another instruction. Then we can use
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// MachineRegisterInfo def / use instead.
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MachineOperand *KillMO = nullptr;
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MachineBasicBlock::iterator KillPos = KillMI;
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++KillPos;
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unsigned NumVisited = 0;
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for (MachineBasicBlock::iterator I = std::next(OldPos); I != KillPos; ++I) {
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MachineInstr *OtherMI = I;
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// DBG_VALUE cannot be counted against the limit.
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if (OtherMI->isDebugValue())
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continue;
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if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
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return false;
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++NumVisited;
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for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = OtherMI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned MOReg = MO.getReg();
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if (!MOReg)
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continue;
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if (DefReg == MOReg)
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return false;
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if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) {
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if (OtherMI == KillMI && MOReg == SavedReg)
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// Save the operand that kills the register. We want to unset the kill
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// marker if we can sink MI past it.
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KillMO = &MO;
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else if (UseRegs.count(MOReg))
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// One of the uses is killed before the destination.
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return false;
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}
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}
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}
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assert(KillMO && "Didn't find kill");
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if (!LIS) {
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// Update kill and LV information.
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KillMO->setIsKill(false);
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KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
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KillMO->setIsKill(true);
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if (LV)
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LV->replaceKillInstruction(SavedReg, KillMI, MI);
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}
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// Move instruction to its destination.
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MBB->remove(MI);
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MBB->insert(KillPos, MI);
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if (LIS)
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LIS->handleMove(MI);
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++Num3AddrSunk;
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return true;
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}
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/// getSingleDef -- return the MachineInstr* if it is the single def of the Reg
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/// in current BB.
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static MachineInstr *getSingleDef(unsigned Reg, MachineBasicBlock *BB,
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const MachineRegisterInfo *MRI) {
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MachineInstr *Ret = nullptr;
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for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
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if (DefMI.getParent() != BB || DefMI.isDebugValue())
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continue;
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if (!Ret)
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Ret = &DefMI;
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else if (Ret != &DefMI)
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return nullptr;
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}
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return Ret;
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}
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/// Check if there is a reversed copy chain from FromReg to ToReg:
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/// %Tmp1 = copy %Tmp2;
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/// %FromReg = copy %Tmp1;
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/// %ToReg = add %FromReg ...
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/// %Tmp2 = copy %ToReg;
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/// MaxLen specifies the maximum length of the copy chain the func
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/// can walk through.
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bool TwoAddressInstructionPass::isRevCopyChain(unsigned FromReg, unsigned ToReg,
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int Maxlen) {
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unsigned TmpReg = FromReg;
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for (int i = 0; i < Maxlen; i++) {
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MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI);
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if (!Def || !Def->isCopy())
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return false;
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TmpReg = Def->getOperand(1).getReg();
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if (TmpReg == ToReg)
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return true;
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}
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return false;
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}
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/// noUseAfterLastDef - Return true if there are no intervening uses between the
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/// last instruction in the MBB that defines the specified register and the
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/// two-address instruction which is being processed. It also returns the last
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/// def location by reference
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bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
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unsigned &LastDef) {
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LastDef = 0;
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unsigned LastUse = Dist;
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for (MachineOperand &MO : MRI->reg_operands(Reg)) {
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MachineInstr *MI = MO.getParent();
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if (MI->getParent() != MBB || MI->isDebugValue())
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continue;
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DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
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if (DI == DistanceMap.end())
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continue;
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if (MO.isUse() && DI->second < LastUse)
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LastUse = DI->second;
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if (MO.isDef() && DI->second > LastDef)
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LastDef = DI->second;
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}
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return !(LastUse > LastDef && LastUse < Dist);
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}
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/// isCopyToReg - Return true if the specified MI is a copy instruction or
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/// a extract_subreg instruction. It also returns the source and destination
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/// registers and whether they are physical registers by reference.
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static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
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unsigned &SrcReg, unsigned &DstReg,
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bool &IsSrcPhys, bool &IsDstPhys) {
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SrcReg = 0;
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DstReg = 0;
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if (MI.isCopy()) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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} else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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} else
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return false;
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IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
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IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
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return true;
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}
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/// isPLainlyKilled - Test if the given register value, which is used by the
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// given instruction, is killed by the given instruction.
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static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
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LiveIntervals *LIS) {
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if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
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!LIS->isNotInMIMap(MI)) {
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// FIXME: Sometimes tryInstructionTransform() will add instructions and
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// test whether they can be folded before keeping them. In this case it
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// sets a kill before recursively calling tryInstructionTransform() again.
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// If there is no interval available, we assume that this instruction is
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// one of those. A kill flag is manually inserted on the operand so the
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// check below will handle it.
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LiveInterval &LI = LIS->getInterval(Reg);
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// This is to match the kill flag version where undefs don't have kill
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// flags.
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if (!LI.hasAtLeastOneValue())
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return false;
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SlotIndex useIdx = LIS->getInstructionIndex(MI);
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LiveInterval::const_iterator I = LI.find(useIdx);
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assert(I != LI.end() && "Reg must be live-in to use.");
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return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
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}
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return MI->killsRegister(Reg);
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}
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/// isKilled - Test if the given register value, which is used by the given
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/// instruction, is killed by the given instruction. This looks through
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/// coalescable copies to see if the original value is potentially not killed.
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///
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/// For example, in this code:
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///
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/// %reg1034 = copy %reg1024
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/// %reg1035 = copy %reg1025<kill>
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/// %reg1036 = add %reg1034<kill>, %reg1035<kill>
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///
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/// %reg1034 is not considered to be killed, since it is copied from a
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/// register which is not killed. Treating it as not killed lets the
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/// normal heuristics commute the (two-address) add, which lets
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/// coalescing eliminate the extra copy.
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///
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/// If allowFalsePositives is true then likely kills are treated as kills even
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/// if it can't be proven that they are kills.
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static bool isKilled(MachineInstr &MI, unsigned Reg,
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const MachineRegisterInfo *MRI,
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const TargetInstrInfo *TII,
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LiveIntervals *LIS,
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bool allowFalsePositives) {
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MachineInstr *DefMI = &MI;
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for (;;) {
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// All uses of physical registers are likely to be kills.
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if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
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(allowFalsePositives || MRI->hasOneUse(Reg)))
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return true;
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if (!isPlainlyKilled(DefMI, Reg, LIS))
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return false;
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return true;
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MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
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// If there are multiple defs, we can't do a simple analysis, so just
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// go with what the kill flag says.
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if (std::next(Begin) != MRI->def_end())
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return true;
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DefMI = Begin->getParent();
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bool IsSrcPhys, IsDstPhys;
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unsigned SrcReg, DstReg;
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// If the def is something other than a copy, then it isn't going to
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// be coalesced, so follow the kill flag.
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if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
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return true;
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Reg = SrcReg;
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}
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}
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/// isTwoAddrUse - Return true if the specified MI uses the specified register
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/// as a two-address use. If so, return the destination register by reference.
|
|
static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
|
|
for (unsigned i = 0, NumOps = MI.getNumOperands(); i != NumOps; ++i) {
|
|
const MachineOperand &MO = MI.getOperand(i);
|
|
if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
|
|
continue;
|
|
unsigned ti;
|
|
if (MI.isRegTiedToDefOperand(i, &ti)) {
|
|
DstReg = MI.getOperand(ti).getReg();
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// findOnlyInterestingUse - Given a register, if has a single in-basic block
|
|
/// use, return the use instruction if it's a copy or a two-address use.
|
|
static
|
|
MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
|
|
MachineRegisterInfo *MRI,
|
|
const TargetInstrInfo *TII,
|
|
bool &IsCopy,
|
|
unsigned &DstReg, bool &IsDstPhys) {
|
|
if (!MRI->hasOneNonDBGUse(Reg))
|
|
// None or more than one use.
|
|
return nullptr;
|
|
MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(Reg);
|
|
if (UseMI.getParent() != MBB)
|
|
return nullptr;
|
|
unsigned SrcReg;
|
|
bool IsSrcPhys;
|
|
if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
|
|
IsCopy = true;
|
|
return &UseMI;
|
|
}
|
|
IsDstPhys = false;
|
|
if (isTwoAddrUse(UseMI, Reg, DstReg)) {
|
|
IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
|
|
return &UseMI;
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
/// getMappedReg - Return the physical register the specified virtual register
|
|
/// might be mapped to.
|
|
static unsigned
|
|
getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
|
|
while (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
|
DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
|
|
if (SI == RegMap.end())
|
|
return 0;
|
|
Reg = SI->second;
|
|
}
|
|
if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
|
return Reg;
|
|
return 0;
|
|
}
|
|
|
|
/// regsAreCompatible - Return true if the two registers are equal or aliased.
|
|
///
|
|
static bool
|
|
regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
|
|
if (RegA == RegB)
|
|
return true;
|
|
if (!RegA || !RegB)
|
|
return false;
|
|
return TRI->regsOverlap(RegA, RegB);
|
|
}
|
|
|
|
|
|
/// isProfitableToCommute - Return true if it's potentially profitable to commute
|
|
/// the two-address instruction that's being processed.
|
|
bool
|
|
TwoAddressInstructionPass::
|
|
isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
|
|
MachineInstr *MI, unsigned Dist) {
|
|
if (OptLevel == CodeGenOpt::None)
|
|
return false;
|
|
|
|
// Determine if it's profitable to commute this two address instruction. In
|
|
// general, we want no uses between this instruction and the definition of
|
|
// the two-address register.
|
|
// e.g.
|
|
// %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
|
|
// %reg1029<def> = MOV8rr %reg1028
|
|
// %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
|
|
// insert => %reg1030<def> = MOV8rr %reg1028
|
|
// %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
|
|
// In this case, it might not be possible to coalesce the second MOV8rr
|
|
// instruction if the first one is coalesced. So it would be profitable to
|
|
// commute it:
|
|
// %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
|
|
// %reg1029<def> = MOV8rr %reg1028
|
|
// %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
|
|
// insert => %reg1030<def> = MOV8rr %reg1029
|
|
// %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
|
|
|
|
if (!isPlainlyKilled(MI, regC, LIS))
|
|
return false;
|
|
|
|
// Ok, we have something like:
|
|
// %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
|
|
// let's see if it's worth commuting it.
|
|
|
|
// Look for situations like this:
|
|
// %reg1024<def> = MOV r1
|
|
// %reg1025<def> = MOV r0
|
|
// %reg1026<def> = ADD %reg1024, %reg1025
|
|
// r0 = MOV %reg1026
|
|
// Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
|
|
unsigned ToRegA = getMappedReg(regA, DstRegMap);
|
|
if (ToRegA) {
|
|
unsigned FromRegB = getMappedReg(regB, SrcRegMap);
|
|
unsigned FromRegC = getMappedReg(regC, SrcRegMap);
|
|
bool CompB = FromRegB && regsAreCompatible(FromRegB, ToRegA, TRI);
|
|
bool CompC = FromRegC && regsAreCompatible(FromRegC, ToRegA, TRI);
|
|
|
|
// Compute if any of the following are true:
|
|
// -RegB is not tied to a register and RegC is compatible with RegA.
|
|
// -RegB is tied to the wrong physical register, but RegC is.
|
|
// -RegB is tied to the wrong physical register, and RegC isn't tied.
|
|
if ((!FromRegB && CompC) || (FromRegB && !CompB && (!FromRegC || CompC)))
|
|
return true;
|
|
// Don't compute if any of the following are true:
|
|
// -RegC is not tied to a register and RegB is compatible with RegA.
|
|
// -RegC is tied to the wrong physical register, but RegB is.
|
|
// -RegC is tied to the wrong physical register, and RegB isn't tied.
|
|
if ((!FromRegC && CompB) || (FromRegC && !CompC && (!FromRegB || CompB)))
|
|
return false;
|
|
}
|
|
|
|
// If there is a use of regC between its last def (could be livein) and this
|
|
// instruction, then bail.
|
|
unsigned LastDefC = 0;
|
|
if (!noUseAfterLastDef(regC, Dist, LastDefC))
|
|
return false;
|
|
|
|
// If there is a use of regB between its last def (could be livein) and this
|
|
// instruction, then go ahead and make this transformation.
|
|
unsigned LastDefB = 0;
|
|
if (!noUseAfterLastDef(regB, Dist, LastDefB))
|
|
return true;
|
|
|
|
// Look for situation like this:
|
|
// %reg101 = MOV %reg100
|
|
// %reg102 = ...
|
|
// %reg103 = ADD %reg102, %reg101
|
|
// ... = %reg103 ...
|
|
// %reg100 = MOV %reg103
|
|
// If there is a reversed copy chain from reg101 to reg103, commute the ADD
|
|
// to eliminate an otherwise unavoidable copy.
|
|
// FIXME:
|
|
// We can extend the logic further: If an pair of operands in an insn has
|
|
// been merged, the insn could be regarded as a virtual copy, and the virtual
|
|
// copy could also be used to construct a copy chain.
|
|
// To more generally minimize register copies, ideally the logic of two addr
|
|
// instruction pass should be integrated with register allocation pass where
|
|
// interference graph is available.
|
|
if (isRevCopyChain(regC, regA, 3))
|
|
return true;
|
|
|
|
if (isRevCopyChain(regB, regA, 3))
|
|
return false;
|
|
|
|
// Since there are no intervening uses for both registers, then commute
|
|
// if the def of regC is closer. Its live interval is shorter.
|
|
return LastDefB && LastDefC && LastDefC > LastDefB;
|
|
}
|
|
|
|
/// commuteInstruction - Commute a two-address instruction and update the basic
|
|
/// block, distance map, and live variables if needed. Return true if it is
|
|
/// successful.
|
|
bool TwoAddressInstructionPass::
|
|
commuteInstruction(MachineBasicBlock::iterator &mi,
|
|
unsigned RegB, unsigned RegC, unsigned Dist) {
|
|
MachineInstr *MI = mi;
|
|
DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
|
|
MachineInstr *NewMI = TII->commuteInstruction(MI);
|
|
|
|
if (NewMI == nullptr) {
|
|
DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
|
|
return false;
|
|
}
|
|
|
|
DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
|
|
assert(NewMI == MI &&
|
|
"TargetInstrInfo::commuteInstruction() should not return a new "
|
|
"instruction unless it was requested.");
|
|
|
|
// Update source register map.
|
|
unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
|
|
if (FromRegC) {
|
|
unsigned RegA = MI->getOperand(0).getReg();
|
|
SrcRegMap[RegA] = FromRegC;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
/// isProfitableToConv3Addr - Return true if it is profitable to convert the
|
|
/// given 2-address instruction to a 3-address one.
|
|
bool
|
|
TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
|
|
// Look for situations like this:
|
|
// %reg1024<def> = MOV r1
|
|
// %reg1025<def> = MOV r0
|
|
// %reg1026<def> = ADD %reg1024, %reg1025
|
|
// r2 = MOV %reg1026
|
|
// Turn ADD into a 3-address instruction to avoid a copy.
|
|
unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
|
|
if (!FromRegB)
|
|
return false;
|
|
unsigned ToRegA = getMappedReg(RegA, DstRegMap);
|
|
return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
|
|
}
|
|
|
|
/// convertInstTo3Addr - Convert the specified two-address instruction into a
|
|
/// three address one. Return true if this transformation was successful.
|
|
bool
|
|
TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
|
|
MachineBasicBlock::iterator &nmi,
|
|
unsigned RegA, unsigned RegB,
|
|
unsigned Dist) {
|
|
// FIXME: Why does convertToThreeAddress() need an iterator reference?
|
|
MachineFunction::iterator MFI = MBB;
|
|
MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
|
|
assert(MBB == MFI && "convertToThreeAddress changed iterator reference");
|
|
if (!NewMI)
|
|
return false;
|
|
|
|
DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
|
|
DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
|
|
bool Sunk = false;
|
|
|
|
if (LIS)
|
|
LIS->ReplaceMachineInstrInMaps(mi, NewMI);
|
|
|
|
if (NewMI->findRegisterUseOperand(RegB, false, TRI))
|
|
// FIXME: Temporary workaround. If the new instruction doesn't
|
|
// uses RegB, convertToThreeAddress must have created more
|
|
// then one instruction.
|
|
Sunk = sink3AddrInstruction(NewMI, RegB, mi);
|
|
|
|
MBB->erase(mi); // Nuke the old inst.
|
|
|
|
if (!Sunk) {
|
|
DistanceMap.insert(std::make_pair(NewMI, Dist));
|
|
mi = NewMI;
|
|
nmi = std::next(mi);
|
|
}
|
|
|
|
// Update source and destination register maps.
|
|
SrcRegMap.erase(RegA);
|
|
DstRegMap.erase(RegB);
|
|
return true;
|
|
}
|
|
|
|
/// scanUses - Scan forward recursively for only uses, update maps if the use
|
|
/// is a copy or a two-address instruction.
|
|
void
|
|
TwoAddressInstructionPass::scanUses(unsigned DstReg) {
|
|
SmallVector<unsigned, 4> VirtRegPairs;
|
|
bool IsDstPhys;
|
|
bool IsCopy = false;
|
|
unsigned NewReg = 0;
|
|
unsigned Reg = DstReg;
|
|
while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
|
|
NewReg, IsDstPhys)) {
|
|
if (IsCopy && !Processed.insert(UseMI).second)
|
|
break;
|
|
|
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
|
|
if (DI != DistanceMap.end())
|
|
// Earlier in the same MBB.Reached via a back edge.
|
|
break;
|
|
|
|
if (IsDstPhys) {
|
|
VirtRegPairs.push_back(NewReg);
|
|
break;
|
|
}
|
|
bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
|
|
if (!isNew)
|
|
assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
|
|
VirtRegPairs.push_back(NewReg);
|
|
Reg = NewReg;
|
|
}
|
|
|
|
if (!VirtRegPairs.empty()) {
|
|
unsigned ToReg = VirtRegPairs.back();
|
|
VirtRegPairs.pop_back();
|
|
while (!VirtRegPairs.empty()) {
|
|
unsigned FromReg = VirtRegPairs.back();
|
|
VirtRegPairs.pop_back();
|
|
bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
|
|
if (!isNew)
|
|
assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
|
|
ToReg = FromReg;
|
|
}
|
|
bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
|
|
if (!isNew)
|
|
assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
|
|
}
|
|
}
|
|
|
|
/// processCopy - If the specified instruction is not yet processed, process it
|
|
/// if it's a copy. For a copy instruction, we find the physical registers the
|
|
/// source and destination registers might be mapped to. These are kept in
|
|
/// point-to maps used to determine future optimizations. e.g.
|
|
/// v1024 = mov r0
|
|
/// v1025 = mov r1
|
|
/// v1026 = add v1024, v1025
|
|
/// r1 = mov r1026
|
|
/// If 'add' is a two-address instruction, v1024, v1026 are both potentially
|
|
/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
|
|
/// potentially joined with r1 on the output side. It's worthwhile to commute
|
|
/// 'add' to eliminate a copy.
|
|
void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
|
|
if (Processed.count(MI))
|
|
return;
|
|
|
|
bool IsSrcPhys, IsDstPhys;
|
|
unsigned SrcReg, DstReg;
|
|
if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
|
|
return;
|
|
|
|
if (IsDstPhys && !IsSrcPhys)
|
|
DstRegMap.insert(std::make_pair(SrcReg, DstReg));
|
|
else if (!IsDstPhys && IsSrcPhys) {
|
|
bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
|
|
if (!isNew)
|
|
assert(SrcRegMap[DstReg] == SrcReg &&
|
|
"Can't map to two src physical registers!");
|
|
|
|
scanUses(DstReg);
|
|
}
|
|
|
|
Processed.insert(MI);
|
|
return;
|
|
}
|
|
|
|
/// rescheduleMIBelowKill - If there is one more local instruction that reads
|
|
/// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
|
|
/// instruction in order to eliminate the need for the copy.
|
|
bool TwoAddressInstructionPass::
|
|
rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
|
|
MachineBasicBlock::iterator &nmi,
|
|
unsigned Reg) {
|
|
// Bail immediately if we don't have LV or LIS available. We use them to find
|
|
// kills efficiently.
|
|
if (!LV && !LIS)
|
|
return false;
|
|
|
|
MachineInstr *MI = &*mi;
|
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
|
|
if (DI == DistanceMap.end())
|
|
// Must be created from unfolded load. Don't waste time trying this.
|
|
return false;
|
|
|
|
MachineInstr *KillMI = nullptr;
|
|
if (LIS) {
|
|
LiveInterval &LI = LIS->getInterval(Reg);
|
|
assert(LI.end() != LI.begin() &&
|
|
"Reg should not have empty live interval.");
|
|
|
|
SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
|
|
LiveInterval::const_iterator I = LI.find(MBBEndIdx);
|
|
if (I != LI.end() && I->start < MBBEndIdx)
|
|
return false;
|
|
|
|
--I;
|
|
KillMI = LIS->getInstructionFromIndex(I->end);
|
|
} else {
|
|
KillMI = LV->getVarInfo(Reg).findKill(MBB);
|
|
}
|
|
if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
|
|
// Don't mess with copies, they may be coalesced later.
|
|
return false;
|
|
|
|
if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
|
|
KillMI->isBranch() || KillMI->isTerminator())
|
|
// Don't move pass calls, etc.
|
|
return false;
|
|
|
|
unsigned DstReg;
|
|
if (isTwoAddrUse(*KillMI, Reg, DstReg))
|
|
return false;
|
|
|
|
bool SeenStore = true;
|
|
if (!MI->isSafeToMove(AA, SeenStore))
|
|
return false;
|
|
|
|
if (TII->getInstrLatency(InstrItins, MI) > 1)
|
|
// FIXME: Needs more sophisticated heuristics.
|
|
return false;
|
|
|
|
SmallSet<unsigned, 2> Uses;
|
|
SmallSet<unsigned, 2> Kills;
|
|
SmallSet<unsigned, 2> Defs;
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (!MO.isReg())
|
|
continue;
|
|
unsigned MOReg = MO.getReg();
|
|
if (!MOReg)
|
|
continue;
|
|
if (MO.isDef())
|
|
Defs.insert(MOReg);
|
|
else {
|
|
Uses.insert(MOReg);
|
|
if (MOReg != Reg && (MO.isKill() ||
|
|
(LIS && isPlainlyKilled(MI, MOReg, LIS))))
|
|
Kills.insert(MOReg);
|
|
}
|
|
}
|
|
|
|
// Move the copies connected to MI down as well.
|
|
MachineBasicBlock::iterator Begin = MI;
|
|
MachineBasicBlock::iterator AfterMI = std::next(Begin);
|
|
|
|
MachineBasicBlock::iterator End = AfterMI;
|
|
while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
|
|
Defs.insert(End->getOperand(0).getReg());
|
|
++End;
|
|
}
|
|
|
|
// Check if the reschedule will not break depedencies.
|
|
unsigned NumVisited = 0;
|
|
MachineBasicBlock::iterator KillPos = KillMI;
|
|
++KillPos;
|
|
for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) {
|
|
MachineInstr *OtherMI = I;
|
|
// DBG_VALUE cannot be counted against the limit.
|
|
if (OtherMI->isDebugValue())
|
|
continue;
|
|
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
|
|
return false;
|
|
++NumVisited;
|
|
if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
|
|
OtherMI->isBranch() || OtherMI->isTerminator())
|
|
// Don't move pass calls, etc.
|
|
return false;
|
|
for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = OtherMI->getOperand(i);
|
|
if (!MO.isReg())
|
|
continue;
|
|
unsigned MOReg = MO.getReg();
|
|
if (!MOReg)
|
|
continue;
|
|
if (MO.isDef()) {
|
|
if (Uses.count(MOReg))
|
|
// Physical register use would be clobbered.
|
|
return false;
|
|
if (!MO.isDead() && Defs.count(MOReg))
|
|
// May clobber a physical register def.
|
|
// FIXME: This may be too conservative. It's ok if the instruction
|
|
// is sunken completely below the use.
|
|
return false;
|
|
} else {
|
|
if (Defs.count(MOReg))
|
|
return false;
|
|
bool isKill = MO.isKill() ||
|
|
(LIS && isPlainlyKilled(OtherMI, MOReg, LIS));
|
|
if (MOReg != Reg &&
|
|
((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
|
|
// Don't want to extend other live ranges and update kills.
|
|
return false;
|
|
if (MOReg == Reg && !isKill)
|
|
// We can't schedule across a use of the register in question.
|
|
return false;
|
|
// Ensure that if this is register in question, its the kill we expect.
|
|
assert((MOReg != Reg || OtherMI == KillMI) &&
|
|
"Found multiple kills of a register in a basic block");
|
|
}
|
|
}
|
|
}
|
|
|
|
// Move debug info as well.
|
|
while (Begin != MBB->begin() && std::prev(Begin)->isDebugValue())
|
|
--Begin;
|
|
|
|
nmi = End;
|
|
MachineBasicBlock::iterator InsertPos = KillPos;
|
|
if (LIS) {
|
|
// We have to move the copies first so that the MBB is still well-formed
|
|
// when calling handleMove().
|
|
for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
|
|
MachineInstr *CopyMI = MBBI;
|
|
++MBBI;
|
|
MBB->splice(InsertPos, MBB, CopyMI);
|
|
LIS->handleMove(CopyMI);
|
|
InsertPos = CopyMI;
|
|
}
|
|
End = std::next(MachineBasicBlock::iterator(MI));
|
|
}
|
|
|
|
// Copies following MI may have been moved as well.
|
|
MBB->splice(InsertPos, MBB, Begin, End);
|
|
DistanceMap.erase(DI);
|
|
|
|
// Update live variables
|
|
if (LIS) {
|
|
LIS->handleMove(MI);
|
|
} else {
|
|
LV->removeVirtualRegisterKilled(Reg, KillMI);
|
|
LV->addVirtualRegisterKilled(Reg, MI);
|
|
}
|
|
|
|
DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
|
|
return true;
|
|
}
|
|
|
|
/// isDefTooClose - Return true if the re-scheduling will put the given
|
|
/// instruction too close to the defs of its register dependencies.
|
|
bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
|
|
MachineInstr *MI) {
|
|
for (MachineInstr &DefMI : MRI->def_instructions(Reg)) {
|
|
if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike())
|
|
continue;
|
|
if (&DefMI == MI)
|
|
return true; // MI is defining something KillMI uses
|
|
DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(&DefMI);
|
|
if (DDI == DistanceMap.end())
|
|
return true; // Below MI
|
|
unsigned DefDist = DDI->second;
|
|
assert(Dist > DefDist && "Visited def already?");
|
|
if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist))
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// rescheduleKillAboveMI - If there is one more local instruction that reads
|
|
/// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
|
|
/// current two-address instruction in order to eliminate the need for the
|
|
/// copy.
|
|
bool TwoAddressInstructionPass::
|
|
rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
|
|
MachineBasicBlock::iterator &nmi,
|
|
unsigned Reg) {
|
|
// Bail immediately if we don't have LV or LIS available. We use them to find
|
|
// kills efficiently.
|
|
if (!LV && !LIS)
|
|
return false;
|
|
|
|
MachineInstr *MI = &*mi;
|
|
DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
|
|
if (DI == DistanceMap.end())
|
|
// Must be created from unfolded load. Don't waste time trying this.
|
|
return false;
|
|
|
|
MachineInstr *KillMI = nullptr;
|
|
if (LIS) {
|
|
LiveInterval &LI = LIS->getInterval(Reg);
|
|
assert(LI.end() != LI.begin() &&
|
|
"Reg should not have empty live interval.");
|
|
|
|
SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
|
|
LiveInterval::const_iterator I = LI.find(MBBEndIdx);
|
|
if (I != LI.end() && I->start < MBBEndIdx)
|
|
return false;
|
|
|
|
--I;
|
|
KillMI = LIS->getInstructionFromIndex(I->end);
|
|
} else {
|
|
KillMI = LV->getVarInfo(Reg).findKill(MBB);
|
|
}
|
|
if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
|
|
// Don't mess with copies, they may be coalesced later.
|
|
return false;
|
|
|
|
unsigned DstReg;
|
|
if (isTwoAddrUse(*KillMI, Reg, DstReg))
|
|
return false;
|
|
|
|
bool SeenStore = true;
|
|
if (!KillMI->isSafeToMove(AA, SeenStore))
|
|
return false;
|
|
|
|
SmallSet<unsigned, 2> Uses;
|
|
SmallSet<unsigned, 2> Kills;
|
|
SmallSet<unsigned, 2> Defs;
|
|
SmallSet<unsigned, 2> LiveDefs;
|
|
for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = KillMI->getOperand(i);
|
|
if (!MO.isReg())
|
|
continue;
|
|
unsigned MOReg = MO.getReg();
|
|
if (MO.isUse()) {
|
|
if (!MOReg)
|
|
continue;
|
|
if (isDefTooClose(MOReg, DI->second, MI))
|
|
return false;
|
|
bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
|
|
if (MOReg == Reg && !isKill)
|
|
return false;
|
|
Uses.insert(MOReg);
|
|
if (isKill && MOReg != Reg)
|
|
Kills.insert(MOReg);
|
|
} else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
|
|
Defs.insert(MOReg);
|
|
if (!MO.isDead())
|
|
LiveDefs.insert(MOReg);
|
|
}
|
|
}
|
|
|
|
// Check if the reschedule will not break depedencies.
|
|
unsigned NumVisited = 0;
|
|
MachineBasicBlock::iterator KillPos = KillMI;
|
|
for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
|
|
MachineInstr *OtherMI = I;
|
|
// DBG_VALUE cannot be counted against the limit.
|
|
if (OtherMI->isDebugValue())
|
|
continue;
|
|
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
|
|
return false;
|
|
++NumVisited;
|
|
if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
|
|
OtherMI->isBranch() || OtherMI->isTerminator())
|
|
// Don't move pass calls, etc.
|
|
return false;
|
|
SmallVector<unsigned, 2> OtherDefs;
|
|
for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = OtherMI->getOperand(i);
|
|
if (!MO.isReg())
|
|
continue;
|
|
unsigned MOReg = MO.getReg();
|
|
if (!MOReg)
|
|
continue;
|
|
if (MO.isUse()) {
|
|
if (Defs.count(MOReg))
|
|
// Moving KillMI can clobber the physical register if the def has
|
|
// not been seen.
|
|
return false;
|
|
if (Kills.count(MOReg))
|
|
// Don't want to extend other live ranges and update kills.
|
|
return false;
|
|
if (OtherMI != MI && MOReg == Reg &&
|
|
!(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))))
|
|
// We can't schedule across a use of the register in question.
|
|
return false;
|
|
} else {
|
|
OtherDefs.push_back(MOReg);
|
|
}
|
|
}
|
|
|
|
for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
|
|
unsigned MOReg = OtherDefs[i];
|
|
if (Uses.count(MOReg))
|
|
return false;
|
|
if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
|
|
LiveDefs.count(MOReg))
|
|
return false;
|
|
// Physical register def is seen.
|
|
Defs.erase(MOReg);
|
|
}
|
|
}
|
|
|
|
// Move the old kill above MI, don't forget to move debug info as well.
|
|
MachineBasicBlock::iterator InsertPos = mi;
|
|
while (InsertPos != MBB->begin() && std::prev(InsertPos)->isDebugValue())
|
|
--InsertPos;
|
|
MachineBasicBlock::iterator From = KillMI;
|
|
MachineBasicBlock::iterator To = std::next(From);
|
|
while (std::prev(From)->isDebugValue())
|
|
--From;
|
|
MBB->splice(InsertPos, MBB, From, To);
|
|
|
|
nmi = std::prev(InsertPos); // Backtrack so we process the moved instr.
|
|
DistanceMap.erase(DI);
|
|
|
|
// Update live variables
|
|
if (LIS) {
|
|
LIS->handleMove(KillMI);
|
|
} else {
|
|
LV->removeVirtualRegisterKilled(Reg, KillMI);
|
|
LV->addVirtualRegisterKilled(Reg, MI);
|
|
}
|
|
|
|
DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
|
|
return true;
|
|
}
|
|
|
|
/// tryInstructionTransform - For the case where an instruction has a single
|
|
/// pair of tied register operands, attempt some transformations that may
|
|
/// either eliminate the tied operands or improve the opportunities for
|
|
/// coalescing away the register copy. Returns true if no copy needs to be
|
|
/// inserted to untie mi's operands (either because they were untied, or
|
|
/// because mi was rescheduled, and will be visited again later). If the
|
|
/// shouldOnlyCommute flag is true, only instruction commutation is attempted.
|
|
bool TwoAddressInstructionPass::
|
|
tryInstructionTransform(MachineBasicBlock::iterator &mi,
|
|
MachineBasicBlock::iterator &nmi,
|
|
unsigned SrcIdx, unsigned DstIdx,
|
|
unsigned Dist, bool shouldOnlyCommute) {
|
|
if (OptLevel == CodeGenOpt::None)
|
|
return false;
|
|
|
|
MachineInstr &MI = *mi;
|
|
unsigned regA = MI.getOperand(DstIdx).getReg();
|
|
unsigned regB = MI.getOperand(SrcIdx).getReg();
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(regB) &&
|
|
"cannot make instruction into two-address form");
|
|
bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(regA))
|
|
scanUses(regA);
|
|
|
|
// Check if it is profitable to commute the operands.
|
|
unsigned SrcOp1, SrcOp2;
|
|
unsigned regC = 0;
|
|
unsigned regCIdx = ~0U;
|
|
bool TryCommute = false;
|
|
bool AggressiveCommute = false;
|
|
if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
|
|
TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
|
|
if (SrcIdx == SrcOp1)
|
|
regCIdx = SrcOp2;
|
|
else if (SrcIdx == SrcOp2)
|
|
regCIdx = SrcOp1;
|
|
|
|
if (regCIdx != ~0U) {
|
|
regC = MI.getOperand(regCIdx).getReg();
|
|
if (!regBKilled && isKilled(MI, regC, MRI, TII, LIS, false))
|
|
// If C dies but B does not, swap the B and C operands.
|
|
// This makes the live ranges of A and C joinable.
|
|
TryCommute = true;
|
|
else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
|
|
TryCommute = true;
|
|
AggressiveCommute = true;
|
|
}
|
|
}
|
|
}
|
|
|
|
// If the instruction is convertible to 3 Addr, instead
|
|
// of returning try 3 Addr transformation aggresively and
|
|
// use this variable to check later. Because it might be better.
|
|
// For example, we can just use `leal (%rsi,%rdi), %eax` and `ret`
|
|
// instead of the following code.
|
|
// addl %esi, %edi
|
|
// movl %edi, %eax
|
|
// ret
|
|
bool Commuted = false;
|
|
|
|
// If it's profitable to commute, try to do so.
|
|
if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
|
|
Commuted = true;
|
|
++NumCommuted;
|
|
if (AggressiveCommute)
|
|
++NumAggrCommuted;
|
|
if (!MI.isConvertibleTo3Addr())
|
|
return false;
|
|
}
|
|
|
|
if (shouldOnlyCommute)
|
|
return false;
|
|
|
|
// If there is one more use of regB later in the same MBB, consider
|
|
// re-schedule this MI below it.
|
|
if (!Commuted && EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
|
|
++NumReSchedDowns;
|
|
return true;
|
|
}
|
|
|
|
if (MI.isConvertibleTo3Addr()) {
|
|
// This instruction is potentially convertible to a true
|
|
// three-address instruction. Check if it is profitable.
|
|
if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
|
|
// Try to convert it.
|
|
if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
|
|
++NumConvertedTo3Addr;
|
|
return true; // Done with this instruction.
|
|
}
|
|
}
|
|
}
|
|
|
|
// Return if it is commuted but 3 addr conversion is failed.
|
|
if (Commuted)
|
|
return false;
|
|
|
|
// If there is one more use of regB later in the same MBB, consider
|
|
// re-schedule it before this MI if it's legal.
|
|
if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
|
|
++NumReSchedUps;
|
|
return true;
|
|
}
|
|
|
|
// If this is an instruction with a load folded into it, try unfolding
|
|
// the load, e.g. avoid this:
|
|
// movq %rdx, %rcx
|
|
// addq (%rax), %rcx
|
|
// in favor of this:
|
|
// movq (%rax), %rcx
|
|
// addq %rdx, %rcx
|
|
// because it's preferable to schedule a load than a register copy.
|
|
if (MI.mayLoad() && !regBKilled) {
|
|
// Determine if a load can be unfolded.
|
|
unsigned LoadRegIndex;
|
|
unsigned NewOpc =
|
|
TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
|
|
/*UnfoldLoad=*/true,
|
|
/*UnfoldStore=*/false,
|
|
&LoadRegIndex);
|
|
if (NewOpc != 0) {
|
|
const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
|
|
if (UnfoldMCID.getNumDefs() == 1) {
|
|
// Unfold the load.
|
|
DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
|
|
const TargetRegisterClass *RC =
|
|
TRI->getAllocatableClass(
|
|
TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
|
|
unsigned Reg = MRI->createVirtualRegister(RC);
|
|
SmallVector<MachineInstr *, 2> NewMIs;
|
|
if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
|
|
/*UnfoldLoad=*/true,/*UnfoldStore=*/false,
|
|
NewMIs)) {
|
|
DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
|
|
return false;
|
|
}
|
|
assert(NewMIs.size() == 2 &&
|
|
"Unfolded a load into multiple instructions!");
|
|
// The load was previously folded, so this is the only use.
|
|
NewMIs[1]->addRegisterKilled(Reg, TRI);
|
|
|
|
// Tentatively insert the instructions into the block so that they
|
|
// look "normal" to the transformation logic.
|
|
MBB->insert(mi, NewMIs[0]);
|
|
MBB->insert(mi, NewMIs[1]);
|
|
|
|
DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
|
|
<< "2addr: NEW INST: " << *NewMIs[1]);
|
|
|
|
// Transform the instruction, now that it no longer has a load.
|
|
unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
|
|
unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
|
|
MachineBasicBlock::iterator NewMI = NewMIs[1];
|
|
bool TransformResult =
|
|
tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
|
|
(void)TransformResult;
|
|
assert(!TransformResult &&
|
|
"tryInstructionTransform() should return false.");
|
|
if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
|
|
// Success, or at least we made an improvement. Keep the unfolded
|
|
// instructions and discard the original.
|
|
if (LV) {
|
|
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI.getOperand(i);
|
|
if (MO.isReg() &&
|
|
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
|
|
if (MO.isUse()) {
|
|
if (MO.isKill()) {
|
|
if (NewMIs[0]->killsRegister(MO.getReg()))
|
|
LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
|
|
else {
|
|
assert(NewMIs[1]->killsRegister(MO.getReg()) &&
|
|
"Kill missing after load unfold!");
|
|
LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
|
|
}
|
|
}
|
|
} else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
|
|
if (NewMIs[1]->registerDefIsDead(MO.getReg()))
|
|
LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
|
|
else {
|
|
assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
|
|
"Dead flag missing after load unfold!");
|
|
LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
|
|
}
|
|
|
|
SmallVector<unsigned, 4> OrigRegs;
|
|
if (LIS) {
|
|
for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
|
|
MOE = MI.operands_end(); MOI != MOE; ++MOI) {
|
|
if (MOI->isReg())
|
|
OrigRegs.push_back(MOI->getReg());
|
|
}
|
|
}
|
|
|
|
MI.eraseFromParent();
|
|
|
|
// Update LiveIntervals.
|
|
if (LIS) {
|
|
MachineBasicBlock::iterator Begin(NewMIs[0]);
|
|
MachineBasicBlock::iterator End(NewMIs[1]);
|
|
LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
|
|
}
|
|
|
|
mi = NewMIs[1];
|
|
} else {
|
|
// Transforming didn't eliminate the tie and didn't lead to an
|
|
// improvement. Clean up the unfolded instructions and keep the
|
|
// original.
|
|
DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
|
|
NewMIs[0]->eraseFromParent();
|
|
NewMIs[1]->eraseFromParent();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
// Collect tied operands of MI that need to be handled.
|
|
// Rewrite trivial cases immediately.
|
|
// Return true if any tied operands where found, including the trivial ones.
|
|
bool TwoAddressInstructionPass::
|
|
collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
|
|
const MCInstrDesc &MCID = MI->getDesc();
|
|
bool AnyOps = false;
|
|
unsigned NumOps = MI->getNumOperands();
|
|
|
|
for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
|
|
unsigned DstIdx = 0;
|
|
if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
|
|
continue;
|
|
AnyOps = true;
|
|
MachineOperand &SrcMO = MI->getOperand(SrcIdx);
|
|
MachineOperand &DstMO = MI->getOperand(DstIdx);
|
|
unsigned SrcReg = SrcMO.getReg();
|
|
unsigned DstReg = DstMO.getReg();
|
|
// Tied constraint already satisfied?
|
|
if (SrcReg == DstReg)
|
|
continue;
|
|
|
|
assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
|
|
|
|
// Deal with <undef> uses immediately - simply rewrite the src operand.
|
|
if (SrcMO.isUndef() && !DstMO.getSubReg()) {
|
|
// Constrain the DstReg register class if required.
|
|
if (TargetRegisterInfo::isVirtualRegister(DstReg))
|
|
if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
|
|
TRI, *MF))
|
|
MRI->constrainRegClass(DstReg, RC);
|
|
SrcMO.setReg(DstReg);
|
|
SrcMO.setSubReg(0);
|
|
DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
|
|
continue;
|
|
}
|
|
TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
|
|
}
|
|
return AnyOps;
|
|
}
|
|
|
|
// Process a list of tied MI operands that all use the same source register.
|
|
// The tied pairs are of the form (SrcIdx, DstIdx).
|
|
void
|
|
TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
|
|
TiedPairList &TiedPairs,
|
|
unsigned &Dist) {
|
|
bool IsEarlyClobber = false;
|
|
for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
|
|
const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
|
|
IsEarlyClobber |= DstMO.isEarlyClobber();
|
|
}
|
|
|
|
bool RemovedKillFlag = false;
|
|
bool AllUsesCopied = true;
|
|
unsigned LastCopiedReg = 0;
|
|
SlotIndex LastCopyIdx;
|
|
unsigned RegB = 0;
|
|
unsigned SubRegB = 0;
|
|
for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
|
|
unsigned SrcIdx = TiedPairs[tpi].first;
|
|
unsigned DstIdx = TiedPairs[tpi].second;
|
|
|
|
const MachineOperand &DstMO = MI->getOperand(DstIdx);
|
|
unsigned RegA = DstMO.getReg();
|
|
|
|
// Grab RegB from the instruction because it may have changed if the
|
|
// instruction was commuted.
|
|
RegB = MI->getOperand(SrcIdx).getReg();
|
|
SubRegB = MI->getOperand(SrcIdx).getSubReg();
|
|
|
|
if (RegA == RegB) {
|
|
// The register is tied to multiple destinations (or else we would
|
|
// not have continued this far), but this use of the register
|
|
// already matches the tied destination. Leave it.
|
|
AllUsesCopied = false;
|
|
continue;
|
|
}
|
|
LastCopiedReg = RegA;
|
|
|
|
assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
|
|
"cannot make instruction into two-address form");
|
|
|
|
#ifndef NDEBUG
|
|
// First, verify that we don't have a use of "a" in the instruction
|
|
// (a = b + a for example) because our transformation will not
|
|
// work. This should never occur because we are in SSA form.
|
|
for (unsigned i = 0; i != MI->getNumOperands(); ++i)
|
|
assert(i == DstIdx ||
|
|
!MI->getOperand(i).isReg() ||
|
|
MI->getOperand(i).getReg() != RegA);
|
|
#endif
|
|
|
|
// Emit a copy.
|
|
MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY), RegA);
|
|
// If this operand is folding a truncation, the truncation now moves to the
|
|
// copy so that the register classes remain valid for the operands.
|
|
MIB.addReg(RegB, 0, SubRegB);
|
|
const TargetRegisterClass *RC = MRI->getRegClass(RegB);
|
|
if (SubRegB) {
|
|
if (TargetRegisterInfo::isVirtualRegister(RegA)) {
|
|
assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),
|
|
SubRegB) &&
|
|
"tied subregister must be a truncation");
|
|
// The superreg class will not be used to constrain the subreg class.
|
|
RC = nullptr;
|
|
}
|
|
else {
|
|
assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))
|
|
&& "tied subregister must be a truncation");
|
|
}
|
|
}
|
|
|
|
// Update DistanceMap.
|
|
MachineBasicBlock::iterator PrevMI = MI;
|
|
--PrevMI;
|
|
DistanceMap.insert(std::make_pair(PrevMI, Dist));
|
|
DistanceMap[MI] = ++Dist;
|
|
|
|
if (LIS) {
|
|
LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot();
|
|
|
|
if (TargetRegisterInfo::isVirtualRegister(RegA)) {
|
|
LiveInterval &LI = LIS->getInterval(RegA);
|
|
VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
|
|
SlotIndex endIdx =
|
|
LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber);
|
|
LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
|
|
}
|
|
}
|
|
|
|
DEBUG(dbgs() << "\t\tprepend:\t" << *MIB);
|
|
|
|
MachineOperand &MO = MI->getOperand(SrcIdx);
|
|
assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
|
|
"inconsistent operand info for 2-reg pass");
|
|
if (MO.isKill()) {
|
|
MO.setIsKill(false);
|
|
RemovedKillFlag = true;
|
|
}
|
|
|
|
// Make sure regA is a legal regclass for the SrcIdx operand.
|
|
if (TargetRegisterInfo::isVirtualRegister(RegA) &&
|
|
TargetRegisterInfo::isVirtualRegister(RegB))
|
|
MRI->constrainRegClass(RegA, RC);
|
|
MO.setReg(RegA);
|
|
// The getMatchingSuper asserts guarantee that the register class projected
|
|
// by SubRegB is compatible with RegA with no subregister. So regardless of
|
|
// whether the dest oper writes a subreg, the source oper should not.
|
|
MO.setSubReg(0);
|
|
|
|
// Propagate SrcRegMap.
|
|
SrcRegMap[RegA] = RegB;
|
|
}
|
|
|
|
|
|
if (AllUsesCopied) {
|
|
if (!IsEarlyClobber) {
|
|
// Replace other (un-tied) uses of regB with LastCopiedReg.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isReg() && MO.getReg() == RegB && MO.getSubReg() == SubRegB &&
|
|
MO.isUse()) {
|
|
if (MO.isKill()) {
|
|
MO.setIsKill(false);
|
|
RemovedKillFlag = true;
|
|
}
|
|
MO.setReg(LastCopiedReg);
|
|
MO.setSubReg(0);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Update live variables for regB.
|
|
if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
|
|
MachineBasicBlock::iterator PrevMI = MI;
|
|
--PrevMI;
|
|
LV->addVirtualRegisterKilled(RegB, PrevMI);
|
|
}
|
|
|
|
// Update LiveIntervals.
|
|
if (LIS) {
|
|
LiveInterval &LI = LIS->getInterval(RegB);
|
|
SlotIndex MIIdx = LIS->getInstructionIndex(MI);
|
|
LiveInterval::const_iterator I = LI.find(MIIdx);
|
|
assert(I != LI.end() && "RegB must be live-in to use.");
|
|
|
|
SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
|
|
if (I->end == UseIdx)
|
|
LI.removeSegment(LastCopyIdx, UseIdx);
|
|
}
|
|
|
|
} else if (RemovedKillFlag) {
|
|
// Some tied uses of regB matched their destination registers, so
|
|
// regB is still used in this instruction, but a kill flag was
|
|
// removed from a different tied use of regB, so now we need to add
|
|
// a kill flag to one of the remaining uses of regB.
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
|
|
MO.setIsKill(true);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// runOnMachineFunction - Reduce two-address instructions to two operands.
|
|
///
|
|
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
|
|
MF = &Func;
|
|
const TargetMachine &TM = MF->getTarget();
|
|
MRI = &MF->getRegInfo();
|
|
TII = MF->getSubtarget().getInstrInfo();
|
|
TRI = MF->getSubtarget().getRegisterInfo();
|
|
InstrItins = MF->getSubtarget().getInstrItineraryData();
|
|
LV = getAnalysisIfAvailable<LiveVariables>();
|
|
LIS = getAnalysisIfAvailable<LiveIntervals>();
|
|
AA = &getAnalysis<AliasAnalysis>();
|
|
OptLevel = TM.getOptLevel();
|
|
|
|
bool MadeChange = false;
|
|
|
|
DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
|
|
DEBUG(dbgs() << "********** Function: "
|
|
<< MF->getName() << '\n');
|
|
|
|
// This pass takes the function out of SSA form.
|
|
MRI->leaveSSA();
|
|
|
|
TiedOperandMap TiedOperands;
|
|
for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
|
|
MBBI != MBBE; ++MBBI) {
|
|
MBB = MBBI;
|
|
unsigned Dist = 0;
|
|
DistanceMap.clear();
|
|
SrcRegMap.clear();
|
|
DstRegMap.clear();
|
|
Processed.clear();
|
|
for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
|
|
mi != me; ) {
|
|
MachineBasicBlock::iterator nmi = std::next(mi);
|
|
if (mi->isDebugValue()) {
|
|
mi = nmi;
|
|
continue;
|
|
}
|
|
|
|
// Expand REG_SEQUENCE instructions. This will position mi at the first
|
|
// expanded instruction.
|
|
if (mi->isRegSequence())
|
|
eliminateRegSequence(mi);
|
|
|
|
DistanceMap.insert(std::make_pair(mi, ++Dist));
|
|
|
|
processCopy(&*mi);
|
|
|
|
// First scan through all the tied register uses in this instruction
|
|
// and record a list of pairs of tied operands for each register.
|
|
if (!collectTiedOperands(mi, TiedOperands)) {
|
|
mi = nmi;
|
|
continue;
|
|
}
|
|
|
|
++NumTwoAddressInstrs;
|
|
MadeChange = true;
|
|
DEBUG(dbgs() << '\t' << *mi);
|
|
|
|
// If the instruction has a single pair of tied operands, try some
|
|
// transformations that may either eliminate the tied operands or
|
|
// improve the opportunities for coalescing away the register copy.
|
|
if (TiedOperands.size() == 1) {
|
|
SmallVectorImpl<std::pair<unsigned, unsigned> > &TiedPairs
|
|
= TiedOperands.begin()->second;
|
|
if (TiedPairs.size() == 1) {
|
|
unsigned SrcIdx = TiedPairs[0].first;
|
|
unsigned DstIdx = TiedPairs[0].second;
|
|
unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
|
|
unsigned DstReg = mi->getOperand(DstIdx).getReg();
|
|
if (SrcReg != DstReg &&
|
|
tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
|
|
// The tied operands have been eliminated or shifted further down the
|
|
// block to ease elimination. Continue processing with 'nmi'.
|
|
TiedOperands.clear();
|
|
mi = nmi;
|
|
continue;
|
|
}
|
|
}
|
|
}
|
|
|
|
// Now iterate over the information collected above.
|
|
for (TiedOperandMap::iterator OI = TiedOperands.begin(),
|
|
OE = TiedOperands.end(); OI != OE; ++OI) {
|
|
processTiedPairs(mi, OI->second, Dist);
|
|
DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
|
|
}
|
|
|
|
// Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
|
|
if (mi->isInsertSubreg()) {
|
|
// From %reg = INSERT_SUBREG %reg, %subreg, subidx
|
|
// To %reg:subidx = COPY %subreg
|
|
unsigned SubIdx = mi->getOperand(3).getImm();
|
|
mi->RemoveOperand(3);
|
|
assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
|
|
mi->getOperand(0).setSubReg(SubIdx);
|
|
mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
|
|
mi->RemoveOperand(1);
|
|
mi->setDesc(TII->get(TargetOpcode::COPY));
|
|
DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
|
|
}
|
|
|
|
// Clear TiedOperands here instead of at the top of the loop
|
|
// since most instructions do not have tied operands.
|
|
TiedOperands.clear();
|
|
mi = nmi;
|
|
}
|
|
}
|
|
|
|
if (LIS)
|
|
MF->verify(this, "After two-address instruction pass");
|
|
|
|
return MadeChange;
|
|
}
|
|
|
|
/// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
|
|
///
|
|
/// The instruction is turned into a sequence of sub-register copies:
|
|
///
|
|
/// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
|
|
///
|
|
/// Becomes:
|
|
///
|
|
/// %dst:ssub0<def,undef> = COPY %v1
|
|
/// %dst:ssub1<def> = COPY %v2
|
|
///
|
|
void TwoAddressInstructionPass::
|
|
eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
|
|
MachineInstr *MI = MBBI;
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
if (MI->getOperand(0).getSubReg() ||
|
|
TargetRegisterInfo::isPhysicalRegister(DstReg) ||
|
|
!(MI->getNumOperands() & 1)) {
|
|
DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
|
|
llvm_unreachable(nullptr);
|
|
}
|
|
|
|
SmallVector<unsigned, 4> OrigRegs;
|
|
if (LIS) {
|
|
OrigRegs.push_back(MI->getOperand(0).getReg());
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2)
|
|
OrigRegs.push_back(MI->getOperand(i).getReg());
|
|
}
|
|
|
|
bool DefEmitted = false;
|
|
for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
|
|
MachineOperand &UseMO = MI->getOperand(i);
|
|
unsigned SrcReg = UseMO.getReg();
|
|
unsigned SubIdx = MI->getOperand(i+1).getImm();
|
|
// Nothing needs to be inserted for <undef> operands.
|
|
if (UseMO.isUndef())
|
|
continue;
|
|
|
|
// Defer any kill flag to the last operand using SrcReg. Otherwise, we
|
|
// might insert a COPY that uses SrcReg after is was killed.
|
|
bool isKill = UseMO.isKill();
|
|
if (isKill)
|
|
for (unsigned j = i + 2; j < e; j += 2)
|
|
if (MI->getOperand(j).getReg() == SrcReg) {
|
|
MI->getOperand(j).setIsKill();
|
|
UseMO.setIsKill(false);
|
|
isKill = false;
|
|
break;
|
|
}
|
|
|
|
// Insert the sub-register copy.
|
|
MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
|
|
TII->get(TargetOpcode::COPY))
|
|
.addReg(DstReg, RegState::Define, SubIdx)
|
|
.addOperand(UseMO);
|
|
|
|
// The first def needs an <undef> flag because there is no live register
|
|
// before it.
|
|
if (!DefEmitted) {
|
|
CopyMI->getOperand(0).setIsUndef(true);
|
|
// Return an iterator pointing to the first inserted instr.
|
|
MBBI = CopyMI;
|
|
}
|
|
DefEmitted = true;
|
|
|
|
// Update LiveVariables' kill info.
|
|
if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
|
|
LV->replaceKillInstruction(SrcReg, MI, CopyMI);
|
|
|
|
DEBUG(dbgs() << "Inserted: " << *CopyMI);
|
|
}
|
|
|
|
MachineBasicBlock::iterator EndMBBI =
|
|
std::next(MachineBasicBlock::iterator(MI));
|
|
|
|
if (!DefEmitted) {
|
|
DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
|
|
MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
|
|
for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
|
|
MI->RemoveOperand(j);
|
|
} else {
|
|
DEBUG(dbgs() << "Eliminated: " << *MI);
|
|
MI->eraseFromParent();
|
|
}
|
|
|
|
// Udpate LiveIntervals.
|
|
if (LIS)
|
|
LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);
|
|
}
|