mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-05 13:30:38 +00:00
b0abb4dc42
the overloaded vector types allowed floating-point or integer vector elements. Most of these operations actually depend on the element type, so bitcasting was not an option. If you include the vpadd intrinsics that I updated earlier, this gets rid of 20 intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78646 91177308-0d34-0410-b5e6-96231b3b80d8
94 lines
2.6 KiB
LLVM
94 lines
2.6 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon | FileCheck %s
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define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vst1i8:
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;CHECK: vst1.8
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1)
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ret void
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}
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define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK: vst1i16:
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;CHECK: vst1.16
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst1.v4i16(i16* %A, <4 x i16> %tmp1)
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ret void
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}
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define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK: vst1i32:
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;CHECK: vst1.32
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst1.v2i32(i32* %A, <2 x i32> %tmp1)
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ret void
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}
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define void @vst1f(float* %A, <2 x float>* %B) nounwind {
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;CHECK: vst1f:
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;CHECK: vst1.32
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst1.v2f32(float* %A, <2 x float> %tmp1)
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ret void
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}
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define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
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;CHECK: vst1i64:
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;CHECK: vst1.64
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%tmp1 = load <1 x i64>* %B
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call void @llvm.arm.neon.vst1.v1i64(i64* %A, <1 x i64> %tmp1)
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ret void
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}
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define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK: vst1Qi8:
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;CHECK: vst1.8
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%tmp1 = load <16 x i8>* %B
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call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1)
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ret void
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}
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define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK: vst1Qi16:
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;CHECK: vst1.16
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vst1.v8i16(i16* %A, <8 x i16> %tmp1)
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ret void
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}
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define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK: vst1Qi32:
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;CHECK: vst1.32
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%tmp1 = load <4 x i32>* %B
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call void @llvm.arm.neon.vst1.v4i32(i32* %A, <4 x i32> %tmp1)
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ret void
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}
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define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
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;CHECK: vst1Qf:
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;CHECK: vst1.32
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%tmp1 = load <4 x float>* %B
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call void @llvm.arm.neon.vst1.v4f32(float* %A, <4 x float> %tmp1)
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ret void
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}
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define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
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;CHECK: vst1Qi64:
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;CHECK: vst1.64
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%tmp1 = load <2 x i64>* %B
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call void @llvm.arm.neon.vst1.v2i64(i64* %A, <2 x i64> %tmp1)
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ret void
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}
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declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>) nounwind
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declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>) nounwind
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declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>) nounwind
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declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>) nounwind
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declare void @llvm.arm.neon.vst1.v1i64(i8*, <1 x i64>) nounwind
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declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>) nounwind
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declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>) nounwind
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declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>) nounwind
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>) nounwind
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declare void @llvm.arm.neon.vst1.v2i64(i8*, <2 x i64>) nounwind
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