mirror of
https://github.com/c64scene-ar/llvm-6502.git
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27b1252c13
This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205541 91177308-0d34-0410-b5e6-96231b3b80d8
131 lines
4.1 KiB
LLVM
131 lines
4.1 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vst1i8:
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;Check the alignment value. Max for this instruction is 64 bits:
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;CHECK: vst1.8 {d16}, [r0:64]
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%tmp1 = load <8 x i8>* %B
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call void @llvm.arm.neon.vst1.v8i8(i8* %A, <8 x i8> %tmp1, i32 16)
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ret void
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}
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define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vst1i16:
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;CHECK: vst1.16
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>* %B
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call void @llvm.arm.neon.vst1.v4i16(i8* %tmp0, <4 x i16> %tmp1, i32 1)
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ret void
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}
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define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vst1i32:
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;CHECK: vst1.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>* %B
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call void @llvm.arm.neon.vst1.v2i32(i8* %tmp0, <2 x i32> %tmp1, i32 1)
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ret void
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}
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define void @vst1f(float* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vst1f:
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;CHECK: vst1.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
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ret void
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}
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;Check for a post-increment updating store.
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define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vst1f_update:
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;CHECK: vst1.32 {d16}, [r1]!
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%A = load float** %ptr
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>* %B
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call void @llvm.arm.neon.vst1.v2f32(i8* %tmp0, <2 x float> %tmp1, i32 1)
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%tmp2 = getelementptr float* %A, i32 2
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store float* %tmp2, float** %ptr
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ret void
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}
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define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
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;CHECK-LABEL: vst1i64:
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;CHECK: vst1.64
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = load <1 x i64>* %B
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call void @llvm.arm.neon.vst1.v1i64(i8* %tmp0, <1 x i64> %tmp1, i32 1)
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ret void
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}
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define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vst1Qi8:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vst1.8 {d16, d17}, [r0:64]
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%tmp1 = load <16 x i8>* %B
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call void @llvm.arm.neon.vst1.v16i8(i8* %A, <16 x i8> %tmp1, i32 8)
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ret void
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}
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define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vst1Qi16:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vst1.16 {d16, d17}, [r0:128]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 32)
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ret void
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}
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;Check for a post-increment updating store with register increment.
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define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
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;CHECK-LABEL: vst1Qi16_update:
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;CHECK: vst1.16 {d16, d17}, [r1:64], r2
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%A = load i16** %ptr
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>* %B
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call void @llvm.arm.neon.vst1.v8i16(i8* %tmp0, <8 x i16> %tmp1, i32 8)
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%tmp2 = getelementptr i16* %A, i32 %inc
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store i16* %tmp2, i16** %ptr
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ret void
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}
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define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vst1Qi32:
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;CHECK: vst1.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>* %B
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call void @llvm.arm.neon.vst1.v4i32(i8* %tmp0, <4 x i32> %tmp1, i32 1)
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ret void
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}
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define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vst1Qf:
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;CHECK: vst1.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>* %B
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call void @llvm.arm.neon.vst1.v4f32(i8* %tmp0, <4 x float> %tmp1, i32 1)
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ret void
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}
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define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: vst1Qi64:
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;CHECK: vst1.64
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = load <2 x i64>* %B
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call void @llvm.arm.neon.vst1.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1)
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ret void
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}
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declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst1.v2f32(i8*, <2 x float>, i32) nounwind
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declare void @llvm.arm.neon.vst1.v1i64(i8*, <1 x i64>, i32) nounwind
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declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
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declare void @llvm.arm.neon.vst1.v2i64(i8*, <2 x i64>, i32) nounwind
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