mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-27 15:29:51 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
39 lines
1.4 KiB
LLVM
39 lines
1.4 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -arm64-simd-scalar=true -asm-verbose=false | FileCheck %s
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;
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define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: bar:
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; CHECK: add.2d v[[REG:[0-9]+]], v0, v1
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; CHECK: add d[[REG3:[0-9]+]], d[[REG]], d1
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; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1
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%add = add <2 x i64> %a, %b
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%vgetq_lane = extractelement <2 x i64> %add, i32 0
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%vgetq_lane2 = extractelement <2 x i64> %b, i32 0
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%add3 = add i64 %vgetq_lane, %vgetq_lane2
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%sub = sub i64 %vgetq_lane, %vgetq_lane2
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%vecinit = insertelement <2 x i64> undef, i64 %add3, i32 0
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%vecinit8 = insertelement <2 x i64> %vecinit, i64 %sub, i32 1
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ret <2 x i64> %vecinit8
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}
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define double @subdd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: subdd_su64:
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; CHECK: sub d0, d1, d0
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; CHECK-NEXT: ret
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%vecext = extractelement <2 x i64> %a, i32 0
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%vecext1 = extractelement <2 x i64> %b, i32 0
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%sub.i = sub nsw i64 %vecext1, %vecext
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%retval = bitcast i64 %sub.i to double
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ret double %retval
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}
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define double @vaddd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
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; CHECK-LABEL: vaddd_su64:
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; CHECK: add d0, d1, d0
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; CHECK-NEXT: ret
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%vecext = extractelement <2 x i64> %a, i32 0
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%vecext1 = extractelement <2 x i64> %b, i32 0
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%add.i = add nsw i64 %vecext1, %vecext
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%retval = bitcast i64 %add.i to double
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ret double %retval
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}
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