mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
60 lines
2.1 KiB
LLVM
60 lines
2.1 KiB
LLVM
; RUN: llc < %s -march=arm64 -mcpu=cyclone | FileCheck %s
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define i128 @shl(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: shl:
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; CHECK: lslv [[XREG_0:x[0-9]+]], x1, x2
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; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40
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; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2
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; CHECK-NEXT: lsrv [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
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; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
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; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64
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; CHECK-NEXT: lslv [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
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; CHECK-NEXT: cmp [[XREG_4]], #0
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; CHECK-NEXT: csel x1, [[XREG_5]], [[XREG_6]], ge
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; CHECK-NEXT: lslv [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
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; CHECK-NEXT: csel x0, xzr, [[SMALLSHIFT_LO]], ge
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; CHECK-NEXT: ret
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%shl = shl i128 %r, %s
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ret i128 %shl
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}
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define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
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; CHECK: ashr:
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; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2
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; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40
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; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2
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; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
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; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
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; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
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; CHECK-NEXT: asrv [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
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; CHECK-NEXT: cmp [[XREG_5]], #0
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; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
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; CHECK-NEXT: asrv [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
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; CHECK-NEXT: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63
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; CHECK-NEXT: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge
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; CHECK-NEXT: ret
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%shr = ashr i128 %r, %s
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ret i128 %shr
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}
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define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
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; CHECK: lshr:
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; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2
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; CHECK-NEXT: orr [[XREG_1:x[0-9]+]], xzr, #0x40
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; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], [[XREG_1]], x2
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; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
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; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
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; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
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; CHECK-NEXT: lsrv [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
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; CHECK-NEXT: cmp [[XREG_5]], #0
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; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
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; CHECK-NEXT: lsrv [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
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; CHECK-NEXT: csel x1, xzr, [[SMALLSHIFT_HI]], ge
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; CHECK-NEXT: ret
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%shr = lshr i128 %r, %s
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ret i128 %shr
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}
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