llvm-6502/test/CodeGen/ARM64/unaligned_ldst.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

42 lines
1.0 KiB
LLVM

; RUN: llc < %s -march=arm64 | FileCheck %s
; rdar://r11231896
define void @t1(i8* nocapture %a, i8* nocapture %b) nounwind {
entry:
; CHECK-LABEL: t1:
; CHECK-NOT: orr
; CHECK: ldr [[X0:x[0-9]+]], [x1]
; CHECK: str [[X0]], [x0]
%tmp1 = bitcast i8* %b to i64*
%tmp2 = bitcast i8* %a to i64*
%tmp3 = load i64* %tmp1, align 1
store i64 %tmp3, i64* %tmp2, align 1
ret void
}
define void @t2(i8* nocapture %a, i8* nocapture %b) nounwind {
entry:
; CHECK-LABEL: t2:
; CHECK-NOT: orr
; CHECK: ldr [[W0:w[0-9]+]], [x1]
; CHECK: str [[W0]], [x0]
%tmp1 = bitcast i8* %b to i32*
%tmp2 = bitcast i8* %a to i32*
%tmp3 = load i32* %tmp1, align 1
store i32 %tmp3, i32* %tmp2, align 1
ret void
}
define void @t3(i8* nocapture %a, i8* nocapture %b) nounwind {
entry:
; CHECK-LABEL: t3:
; CHECK-NOT: orr
; CHECK: ldrh [[W0:w[0-9]+]], [x1]
; CHECK: strh [[W0]], [x0]
%tmp1 = bitcast i8* %b to i16*
%tmp2 = bitcast i8* %a to i16*
%tmp3 = load i16* %tmp1, align 1
store i16 %tmp3, i16* %tmp2, align 1
ret void
}