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ab849adec4
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.
The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).
Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that. The assembler and disassembler
are fully implemented and tested. However:
- CodeGen support causes miscompiles; test-suite runtime failures:
MultiSource/Benchmarks/FreeBench/distray/distray
MultiSource/Benchmarks/McCat/08-main/main
MultiSource/Benchmarks/Olden/voronoi/voronoi
MultiSource/Benchmarks/mafft/pairlocalalign
MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
SingleSource/Benchmarks/CoyoteBench/almabench
SingleSource/Benchmarks/Misc/matmul_f64_4x4
- The lowering currently falls back to using Altivec instructions far more
than it should. Worse, there are some things that are scalarized through the
stack that shouldn't be.
- A lot of unnecessary copies make it past the optimizers, and this needs to
be fixed.
- Many more regression tests are needed.
Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203768 91177308-0d34-0410-b5e6-96231b3b80d8
64 lines
2.3 KiB
C++
64 lines
2.3 KiB
C++
//===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an PPC MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PPCINSTPRINTER_H
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#define PPCINSTPRINTER_H
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#include "llvm/MC/MCInstPrinter.h"
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namespace llvm {
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class MCOperand;
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class PPCInstPrinter : public MCInstPrinter {
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bool IsDarwin;
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public:
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PPCInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI, bool isDarwin)
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: MCInstPrinter(MAI, MII, MRI), IsDarwin(isDarwin) {}
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bool isDarwinSyntax() const {
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return IsDarwin;
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}
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virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
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virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printPredicateOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, const char *Modifier = 0);
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void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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};
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} // end namespace llvm
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#endif
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