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https://github.com/c64scene-ar/llvm-6502.git
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3b2e5e619e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13126 91177308-0d34-0410-b5e6-96231b3b80d8
121 lines
3.8 KiB
C++
121 lines
3.8 KiB
C++
//===-- SparcV9Internals.h ----------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines stuff that is to be private to the SparcV9 backend, but is
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// shared among different portions of the backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARC_INTERNALS_H
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#define SPARC_INTERNALS_H
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetSchedInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "SparcV9RegInfo.h"
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#include "llvm/Type.h"
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#include "SparcV9RegClassInfo.h"
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#include "Config/sys/types.h"
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namespace llvm {
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class LiveRange;
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class SparcV9TargetMachine;
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class Pass;
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enum SparcV9InstrSchedClass {
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SPARC_NONE, /* Instructions with no scheduling restrictions */
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SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
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SPARC_IEU0, /* Integer class IEU0 */
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SPARC_IEU1, /* Integer class IEU1 */
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SPARC_FPM, /* FP Multiply or Divide instructions */
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SPARC_FPA, /* All other FP instructions */
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SPARC_CTI, /* Control-transfer instructions */
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SPARC_LD, /* Load instructions */
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SPARC_ST, /* Store instructions */
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SPARC_SINGLE, /* Instructions that must issue by themselves */
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SPARC_INV, /* This should stay at the end for the next value */
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SPARC_NUM_SCHED_CLASSES = SPARC_INV
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};
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//---------------------------------------------------------------------------
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// enum SparcV9MachineOpCode.
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// const TargetInstrDescriptor SparcV9MachineInstrDesc[]
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//
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// Purpose:
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// Description of UltraSparcV9 machine instructions.
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//
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//---------------------------------------------------------------------------
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namespace V9 {
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enum SparcV9MachineOpCode {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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ENUM,
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#include "SparcV9Instr.def"
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// End-of-array marker
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INVALID_OPCODE,
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NUM_REAL_OPCODES = PHI, // number of valid opcodes
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NUM_TOTAL_OPCODES = INVALID_OPCODE
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};
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}
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// Array of machine instruction descriptions...
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extern const TargetInstrDescriptor SparcV9MachineInstrDesc[];
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//---------------------------------------------------------------------------
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// class SparcV9SchedInfo
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//
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// Purpose:
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// Interface to instruction scheduling information for UltraSPARC.
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// The parameter values above are based on UltraSPARC IIi.
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//---------------------------------------------------------------------------
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class SparcV9SchedInfo: public TargetSchedInfo {
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public:
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SparcV9SchedInfo(const TargetMachine &tgt);
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protected:
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virtual void initializeResources();
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};
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/// createStackSlotsPass - External interface to stack-slots pass that enters 2
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/// empty slots at the top of each function stack
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///
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Pass *createStackSlotsPass(const TargetMachine &TM);
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/// Specializes LLVM code for a target machine.
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///
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FunctionPass *createPreSelectionPass(const TargetMachine &TM);
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/// Peephole optimization pass operating on machine code
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///
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FunctionPass *createPeepholeOptsPass(const TargetMachine &TM);
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/// Writes out assembly code for the module, one function at a time
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///
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FunctionPass *createAsmPrinterPass(std::ostream &Out, const TargetMachine &TM);
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/// getPrologEpilogInsertionPass - Inserts prolog/epilog code.
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///
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FunctionPass* createPrologEpilogInsertionPass();
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/// getBytecodeAsmPrinterPass - Emits final LLVM bytecode to assembly file.
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///
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Pass* createBytecodeAsmPrinterPass(std::ostream &Out);
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FunctionPass *createSparcV9MachineCodeDestructionPass();
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} // End llvm namespace
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#endif
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