llvm-6502/test/CodeGen/Hexagon/fusedandshift.ll
Sirish Pande 26f61a158b Support for target dependent Hexagon VLIW packetizer.
This patch creates and optimizes packets as per Hexagon ISA rules.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-03 21:52:53 +00:00

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451 B
LLVM

; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
; Check that we generate fused logical and with shift instruction.
; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}})
define i32 @main(i16* %a, i16* %b) nounwind {
entry:
%0 = load i16* %a, align 2
%conv1 = sext i16 %0 to i32
%shr1 = ashr i32 %conv1, 3
%and1 = and i32 %shr1, 15
%conv2 = trunc i32 %and1 to i16
store i16 %conv2, i16* %b, align 2
ret i32 0
}