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https://github.com/c64scene-ar/llvm-6502.git
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8ba732bb1c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23610 91177308-0d34-0410-b5e6-96231b3b80d8
1157 lines
38 KiB
C++
1157 lines
38 KiB
C++
//===-- ScheduleDAG.cpp - Implement a trivial DAG scheduler ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements a simple two pass scheduler. The first pass attempts to push
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// backward any lengthy instructions and critical paths. The second pass packs
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// instructions into semi-optimal time slots.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "sched"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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// Style of scheduling to use.
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enum ScheduleChoices {
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noScheduling,
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simpleScheduling,
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};
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} // namespace
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cl::opt<ScheduleChoices> ScheduleStyle("sched",
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cl::desc("Choose scheduling style"),
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cl::init(noScheduling),
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cl::values(
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clEnumValN(noScheduling, "none",
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"Trivial emission with no analysis"),
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clEnumValN(simpleScheduling, "simple",
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"Minimize critical path and maximize processor utilization"),
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clEnumValEnd));
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#ifndef NDEBUG
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static cl::opt<bool>
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ViewDAGs("view-sched-dags", cl::Hidden,
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cl::desc("Pop up a window to show sched dags as they are processed"));
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#else
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static const bool ViewDAGs = 0;
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#endif
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namespace {
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//===----------------------------------------------------------------------===//
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///
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/// BitsIterator - Provides iteration through individual bits in a bit vector.
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///
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template<class T>
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class BitsIterator {
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private:
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T Bits; // Bits left to iterate through
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public:
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/// Ctor.
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BitsIterator(T Initial) : Bits(Initial) {}
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/// Next - Returns the next bit set or zero if exhausted.
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inline T Next() {
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// Get the rightmost bit set
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T Result = Bits & -Bits;
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// Remove from rest
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Bits &= ~Result;
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// Return single bit or zero
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return Result;
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}
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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///
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/// ResourceTally - Manages the use of resources over time intervals. Each
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/// item (slot) in the tally vector represents the resources used at a given
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/// moment. A bit set to 1 indicates that a resource is in use, otherwise
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/// available. An assumption is made that the tally is large enough to schedule
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/// all current instructions (asserts otherwise.)
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///
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template<class T>
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class ResourceTally {
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private:
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std::vector<T> Tally; // Resources used per slot
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typedef typename std::vector<T>::iterator Iter;
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// Tally iterator
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/// AllInUse - Test to see if all of the resources in the slot are busy (set.)
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inline bool AllInUse(Iter Cursor, unsigned ResourceSet) {
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return (*Cursor & ResourceSet) == ResourceSet;
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}
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/// Skip - Skip over slots that use all of the specified resource (all are
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/// set.)
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Iter Skip(Iter Cursor, unsigned ResourceSet) {
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assert(ResourceSet && "At least one resource bit needs to bet set");
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// Continue to the end
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while (true) {
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// Break out if one of the resource bits is not set
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if (!AllInUse(Cursor, ResourceSet)) return Cursor;
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// Try next slot
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Cursor++;
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assert(Cursor < Tally.end() && "Tally is not large enough for schedule");
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}
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}
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/// FindSlots - Starting from Begin, locate N consecutive slots where at least
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/// one of the resource bits is available. Returns the address of first slot.
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Iter FindSlots(Iter Begin, unsigned N, unsigned ResourceSet,
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unsigned &Resource) {
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// Track position
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Iter Cursor = Begin;
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// Try all possible slots forward
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while (true) {
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// Skip full slots
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Cursor = Skip(Cursor, ResourceSet);
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// Determine end of interval
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Iter End = Cursor + N;
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assert(End <= Tally.end() && "Tally is not large enough for schedule");
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// Iterate thru each resource
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BitsIterator<T> Resources(ResourceSet & ~*Cursor);
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while (unsigned Res = Resources.Next()) {
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// Check if resource is available for next N slots
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// Break out if resource is busy
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Iter Interval = Cursor;
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for (; Interval < End && !(*Interval & Res); Interval++) {}
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// If available for interval, return where and which resource
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if (Interval == End) {
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Resource = Res;
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return Cursor;
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}
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// Otherwise, check if worth checking other resources
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if (AllInUse(Interval, ResourceSet)) {
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// Start looking beyond interval
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Cursor = Interval;
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break;
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}
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}
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Cursor++;
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}
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}
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/// Reserve - Mark busy (set) the specified N slots.
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void Reserve(Iter Begin, unsigned N, unsigned Resource) {
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// Determine end of interval
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Iter End = Begin + N;
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assert(End <= Tally.end() && "Tally is not large enough for schedule");
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// Set resource bit in each slot
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for (; Begin < End; Begin++)
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*Begin |= Resource;
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}
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public:
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/// Initialize - Resize and zero the tally to the specified number of time
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/// slots.
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inline void Initialize(unsigned N) {
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Tally.assign(N, 0); // Initialize tally to all zeros.
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}
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// FindAndReserve - Locate and mark busy (set) N bits started at slot I, using
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// ResourceSet for choices.
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unsigned FindAndReserve(unsigned I, unsigned N, unsigned ResourceSet) {
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// Which resource used
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unsigned Resource;
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// Find slots for instruction.
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Iter Where = FindSlots(Tally.begin() + I, N, ResourceSet, Resource);
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// Reserve the slots
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Reserve(Where, N, Resource);
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// Return time slot (index)
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return Where - Tally.begin();
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}
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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///
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/// Node group - This struct is used to manage flagged node groups.
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///
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class NodeInfo;
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class NodeGroup : public std::vector<NodeInfo *> {
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private:
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int Pending; // Number of visits pending before
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// adding to order
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public:
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// Ctor.
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NodeGroup() : Pending(0) {}
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// Accessors
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inline NodeInfo *getLeader() { return empty() ? NULL : front(); }
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inline int getPending() const { return Pending; }
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inline void setPending(int P) { Pending = P; }
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inline int addPending(int I) { return Pending += I; }
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static void Add(NodeInfo *D, NodeInfo *U);
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static unsigned CountInternalUses(NodeInfo *D, NodeInfo *U);
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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///
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/// NodeInfo - This struct tracks information used to schedule the a node.
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///
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class NodeInfo {
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private:
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int Pending; // Number of visits pending before
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// adding to order
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public:
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SDNode *Node; // DAG node
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unsigned Latency; // Cycles to complete instruction
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unsigned ResourceSet; // Bit vector of usable resources
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unsigned Slot; // Node's time slot
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NodeGroup *Group; // Grouping information
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unsigned VRBase; // Virtual register base
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// Ctor.
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NodeInfo(SDNode *N = NULL)
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: Pending(0)
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, Node(N)
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, Latency(0)
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, ResourceSet(0)
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, Slot(0)
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, Group(NULL)
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, VRBase(0)
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{}
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// Accessors
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inline bool isInGroup() const {
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assert(!Group || !Group->empty() && "Group with no members");
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return Group != NULL;
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}
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inline bool isGroupLeader() const {
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return isInGroup() && Group->getLeader() == this;
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}
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inline int getPending() const {
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return Group ? Group->getPending() : Pending;
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}
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inline void setPending(int P) {
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if (Group) Group->setPending(P);
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else Pending = P;
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}
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inline int addPending(int I) {
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if (Group) return Group->addPending(I);
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else return Pending += I;
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}
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};
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typedef std::vector<NodeInfo *>::iterator NIIterator;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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///
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/// NodeGroupIterator - Iterates over all the nodes indicated by the node info.
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/// If the node is in a group then iterate over the members of the group,
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/// otherwise just the node info.
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///
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class NodeGroupIterator {
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private:
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NodeInfo *NI; // Node info
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NIIterator NGI; // Node group iterator
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NIIterator NGE; // Node group iterator end
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public:
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// Ctor.
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NodeGroupIterator(NodeInfo *N) : NI(N) {
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// If the node is in a group then set up the group iterator. Otherwise
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// the group iterators will trip first time out.
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if (N->isInGroup()) {
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// get Group
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NodeGroup *Group = NI->Group;
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NGI = Group->begin();
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NGE = Group->end();
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// Prevent this node from being used (will be in members list
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NI = NULL;
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}
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}
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/// next - Return the next node info, otherwise NULL.
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///
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NodeInfo *next() {
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// If members list
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if (NGI != NGE) return *NGI++;
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// Use node as the result (may be NULL)
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NodeInfo *Result = NI;
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// Only use once
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NI = NULL;
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// Return node or NULL
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return Result;
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}
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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///
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/// NodeGroupOpIterator - Iterates over all the operands of a node. If the node
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/// is a member of a group, this iterates over all the operands of all the
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/// members of the group.
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///
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class NodeGroupOpIterator {
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private:
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NodeInfo *NI; // Node containing operands
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NodeGroupIterator GI; // Node group iterator
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SDNode::op_iterator OI; // Operand iterator
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SDNode::op_iterator OE; // Operand iterator end
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/// CheckNode - Test if node has more operands. If not get the next node
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/// skipping over nodes that have no operands.
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void CheckNode() {
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// Only if operands are exhausted first
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while (OI == OE) {
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// Get next node info
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NodeInfo *NI = GI.next();
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// Exit if nodes are exhausted
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if (!NI) return;
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// Get node itself
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SDNode *Node = NI->Node;
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// Set up the operand iterators
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OI = Node->op_begin();
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OE = Node->op_end();
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}
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}
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public:
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// Ctor.
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NodeGroupOpIterator(NodeInfo *N) : NI(N), GI(N) {}
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/// isEnd - Returns true when not more operands are available.
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///
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inline bool isEnd() { CheckNode(); return OI == OE; }
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/// next - Returns the next available operand.
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///
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inline SDOperand next() {
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assert(OI != OE && "Not checking for end of NodeGroupOpIterator correctly");
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return *OI++;
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}
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};
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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///
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/// SimpleSched - Simple two pass scheduler.
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///
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class SimpleSched {
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private:
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// TODO - get ResourceSet from TII
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enum {
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RSInteger = 0x3, // Two integer units
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RSFloat = 0xC, // Two float units
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RSLoadStore = 0x30, // Two load store units
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RSOther = 0 // Processing unit independent
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};
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MachineBasicBlock *BB; // Current basic block
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SelectionDAG &DAG; // DAG of the current basic block
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const TargetMachine &TM; // Target processor
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const TargetInstrInfo &TII; // Target instruction information
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const MRegisterInfo &MRI; // Target processor register information
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SSARegMap *RegMap; // Virtual/real register map
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MachineConstantPool *ConstPool; // Target constant pool
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unsigned NodeCount; // Number of nodes in DAG
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NodeInfo *Info; // Info for nodes being scheduled
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std::map<SDNode *, NodeInfo *> Map; // Map nodes to info
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std::vector<NodeInfo*> Ordering; // Emit ordering of nodes
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ResourceTally<unsigned> Tally; // Resource usage tally
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unsigned NSlots; // Total latency
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static const unsigned NotFound = ~0U; // Search marker
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public:
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// Ctor.
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SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
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: BB(bb), DAG(D), TM(D.getTarget()), TII(*TM.getInstrInfo()),
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MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()),
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ConstPool(BB->getParent()->getConstantPool()),
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NSlots(0) {
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assert(&TII && "Target doesn't provide instr info?");
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assert(&MRI && "Target doesn't provide register info?");
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}
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// Run - perform scheduling.
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MachineBasicBlock *Run() {
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Schedule();
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return BB;
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}
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private:
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/// getNI - Returns the node info for the specified node.
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///
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inline NodeInfo *getNI(SDNode *Node) { return Map[Node]; }
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/// getVR - Returns the virtual register number of the node.
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///
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inline unsigned getVR(SDOperand Op) {
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NodeInfo *NI = getNI(Op.Val);
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assert(NI->VRBase != 0 && "Node emitted out of order - late");
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return NI->VRBase + Op.ResNo;
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}
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static bool isFlagDefiner(SDNode *A);
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static bool isFlagUser(SDNode *A);
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static bool isDefiner(NodeInfo *A, NodeInfo *B);
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static bool isPassiveNode(SDNode *Node);
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void IncludeNode(NodeInfo *NI);
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void VisitAll();
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void Schedule();
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void IdentifyGroups();
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void GatherSchedulingInfo();
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void PrepareNodeInfo();
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bool isStrongDependency(NodeInfo *A, NodeInfo *B);
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bool isWeakDependency(NodeInfo *A, NodeInfo *B);
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void ScheduleBackward();
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void ScheduleForward();
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void EmitAll();
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void EmitNode(NodeInfo *NI);
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static unsigned CountResults(SDNode *Node);
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static unsigned CountOperands(SDNode *Node);
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unsigned CreateVirtualRegisters(MachineInstr *MI,
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unsigned NumResults,
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const TargetInstrDescriptor &II);
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unsigned EmitDAG(SDOperand A);
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void printSI(std::ostream &O, NodeInfo *NI) const;
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void print(std::ostream &O) const;
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inline void dump(const char *tag) const { std::cerr << tag; dump(); }
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void dump() const;
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};
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//===----------------------------------------------------------------------===//
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} // namespace
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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/// Add - Adds a definer and user pair to a node group.
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///
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void NodeGroup::Add(NodeInfo *D, NodeInfo *U) {
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// Get current groups
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NodeGroup *DGroup = D->Group;
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NodeGroup *UGroup = U->Group;
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// If both are members of groups
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if (DGroup && UGroup) {
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// There may have been another edge connecting
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if (DGroup == UGroup) return;
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// Add the pending users count
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DGroup->addPending(UGroup->getPending());
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// For each member of the users group
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NodeGroupIterator UNGI(U);
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while (NodeInfo *UNI = UNGI.next() ) {
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// Change the group
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UNI->Group = DGroup;
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// For each member of the definers group
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NodeGroupIterator DNGI(D);
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while (NodeInfo *DNI = DNGI.next() ) {
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// Remove internal edges
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DGroup->addPending(-CountInternalUses(DNI, UNI));
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}
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}
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// Merge the two lists
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DGroup->insert(DGroup->end(), UGroup->begin(), UGroup->end());
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} else if (DGroup) {
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// Make user member of definers group
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U->Group = DGroup;
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// Add users uses to definers group pending
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DGroup->addPending(U->Node->use_size());
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// For each member of the definers group
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NodeGroupIterator DNGI(D);
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while (NodeInfo *DNI = DNGI.next() ) {
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// Remove internal edges
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DGroup->addPending(-CountInternalUses(DNI, U));
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}
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DGroup->push_back(U);
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} else if (UGroup) {
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// Make definer member of users group
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D->Group = UGroup;
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// Add definers uses to users group pending
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UGroup->addPending(D->Node->use_size());
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// For each member of the users group
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NodeGroupIterator UNGI(U);
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while (NodeInfo *UNI = UNGI.next() ) {
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// Remove internal edges
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UGroup->addPending(-CountInternalUses(D, UNI));
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}
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UGroup->insert(UGroup->begin(), D);
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} else {
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D->Group = U->Group = DGroup = new NodeGroup();
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DGroup->addPending(D->Node->use_size() + U->Node->use_size() -
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CountInternalUses(D, U));
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DGroup->push_back(D);
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DGroup->push_back(U);
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}
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}
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/// CountInternalUses - Returns the number of edges between the two nodes.
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///
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unsigned NodeGroup::CountInternalUses(NodeInfo *D, NodeInfo *U) {
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unsigned N = 0;
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for (SDNode:: use_iterator UI = D->Node->use_begin(),
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E = D->Node->use_end(); UI != E; UI++) {
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if (*UI == U->Node) N++;
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}
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return N;
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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/// isFlagDefiner - Returns true if the node defines a flag result.
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bool SimpleSched::isFlagDefiner(SDNode *A) {
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unsigned N = A->getNumValues();
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return N && A->getValueType(N - 1) == MVT::Flag;
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}
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/// isFlagUser - Returns true if the node uses a flag result.
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|
///
|
|
bool SimpleSched::isFlagUser(SDNode *A) {
|
|
unsigned N = A->getNumOperands();
|
|
return N && A->getOperand(N - 1).getValueType() == MVT::Flag;
|
|
}
|
|
|
|
/// isDefiner - Return true if node A is a definer for B.
|
|
///
|
|
bool SimpleSched::isDefiner(NodeInfo *A, NodeInfo *B) {
|
|
// While there are A nodes
|
|
NodeGroupIterator NII(A);
|
|
while (NodeInfo *NI = NII.next()) {
|
|
// Extract node
|
|
SDNode *Node = NI->Node;
|
|
// While there operands in nodes of B
|
|
NodeGroupOpIterator NGOI(B);
|
|
while (!NGOI.isEnd()) {
|
|
SDOperand Op = NGOI.next();
|
|
// If node from A defines a node in B
|
|
if (Node == Op.Val) return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/// isPassiveNode - Return true if the node is a non-scheduled leaf.
|
|
///
|
|
bool SimpleSched::isPassiveNode(SDNode *Node) {
|
|
if (isa<ConstantSDNode>(Node)) return true;
|
|
if (isa<RegisterSDNode>(Node)) return true;
|
|
if (isa<GlobalAddressSDNode>(Node)) return true;
|
|
if (isa<BasicBlockSDNode>(Node)) return true;
|
|
if (isa<FrameIndexSDNode>(Node)) return true;
|
|
if (isa<ConstantPoolSDNode>(Node)) return true;
|
|
if (isa<ExternalSymbolSDNode>(Node)) return true;
|
|
return false;
|
|
}
|
|
|
|
/// IncludeNode - Add node to NodeInfo vector.
|
|
///
|
|
void SimpleSched::IncludeNode(NodeInfo *NI) {
|
|
// Get node
|
|
SDNode *Node = NI->Node;
|
|
// Ignore entry node
|
|
if (Node->getOpcode() == ISD::EntryToken) return;
|
|
// Check current count for node
|
|
int Count = NI->getPending();
|
|
// If the node is already in list
|
|
if (Count < 0) return;
|
|
// Decrement count to indicate a visit
|
|
Count--;
|
|
// If count has gone to zero then add node to list
|
|
if (!Count) {
|
|
// Add node
|
|
if (NI->isInGroup()) {
|
|
Ordering.push_back(NI->Group->getLeader());
|
|
} else {
|
|
Ordering.push_back(NI);
|
|
}
|
|
// indicate node has been added
|
|
Count--;
|
|
}
|
|
// Mark as visited with new count
|
|
NI->setPending(Count);
|
|
}
|
|
|
|
/// VisitAll - Visit each node breadth-wise to produce an initial ordering.
|
|
/// Note that the ordering in the Nodes vector is reversed.
|
|
void SimpleSched::VisitAll() {
|
|
// Add first element to list
|
|
Ordering.push_back(getNI(DAG.getRoot().Val));
|
|
|
|
// Iterate through all nodes that have been added
|
|
for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
|
|
// Visit all operands
|
|
NodeGroupOpIterator NGI(Ordering[i]);
|
|
while (!NGI.isEnd()) {
|
|
// Get next operand
|
|
SDOperand Op = NGI.next();
|
|
// Get node
|
|
SDNode *Node = Op.Val;
|
|
// Ignore passive nodes
|
|
if (isPassiveNode(Node)) continue;
|
|
// Check out node
|
|
IncludeNode(getNI(Node));
|
|
}
|
|
}
|
|
|
|
// Add entry node last (IncludeNode filters entry nodes)
|
|
if (DAG.getEntryNode().Val != DAG.getRoot().Val)
|
|
Ordering.push_back(getNI(DAG.getEntryNode().Val));
|
|
|
|
// FIXME - Reverse the order
|
|
for (unsigned i = 0, N = Ordering.size(), Half = N >> 1; i < Half; i++) {
|
|
unsigned j = N - i - 1;
|
|
NodeInfo *tmp = Ordering[i];
|
|
Ordering[i] = Ordering[j];
|
|
Ordering[j] = tmp;
|
|
}
|
|
}
|
|
|
|
/// IdentifyGroups - Put flagged nodes into groups.
|
|
///
|
|
void SimpleSched::IdentifyGroups() {
|
|
for (unsigned i = 0, N = NodeCount; i < N; i++) {
|
|
NodeInfo* NI = &Info[i];
|
|
SDNode *Node = NI->Node;
|
|
|
|
// For each operand (in reverse to only look at flags)
|
|
for (unsigned N = Node->getNumOperands(); 0 < N--;) {
|
|
// Get operand
|
|
SDOperand Op = Node->getOperand(N);
|
|
// No more flags to walk
|
|
if (Op.getValueType() != MVT::Flag) break;
|
|
// Add to node group
|
|
NodeGroup::Add(getNI(Op.Val), NI);
|
|
}
|
|
}
|
|
}
|
|
|
|
/// GatherSchedulingInfo - Get latency and resource information about each node.
|
|
///
|
|
void SimpleSched::GatherSchedulingInfo() {
|
|
for (unsigned i = 0, N = NodeCount; i < N; i++) {
|
|
NodeInfo* NI = &Info[i];
|
|
SDNode *Node = NI->Node;
|
|
|
|
MVT::ValueType VT = Node->getValueType(0);
|
|
|
|
if (Node->isTargetOpcode()) {
|
|
MachineOpCode TOpc = Node->getTargetOpcode();
|
|
// FIXME: This is an ugly (but temporary!) hack to test the scheduler
|
|
// before we have real target info.
|
|
// FIXME NI->Latency = std::max(1, TII.maxLatency(TOpc));
|
|
// FIXME NI->ResourceSet = TII.resources(TOpc);
|
|
if (TII.isCall(TOpc)) {
|
|
NI->ResourceSet = RSInteger;
|
|
NI->Latency = 40;
|
|
} else if (TII.isLoad(TOpc)) {
|
|
NI->ResourceSet = RSLoadStore;
|
|
NI->Latency = 5;
|
|
} else if (TII.isStore(TOpc)) {
|
|
NI->ResourceSet = RSLoadStore;
|
|
NI->Latency = 2;
|
|
} else if (MVT::isInteger(VT)) {
|
|
NI->ResourceSet = RSInteger;
|
|
NI->Latency = 2;
|
|
} else if (MVT::isFloatingPoint(VT)) {
|
|
NI->ResourceSet = RSFloat;
|
|
NI->Latency = 3;
|
|
} else {
|
|
NI->ResourceSet = RSOther;
|
|
NI->Latency = 0;
|
|
}
|
|
} else {
|
|
if (MVT::isInteger(VT)) {
|
|
NI->ResourceSet = RSInteger;
|
|
NI->Latency = 2;
|
|
} else if (MVT::isFloatingPoint(VT)) {
|
|
NI->ResourceSet = RSFloat;
|
|
NI->Latency = 3;
|
|
} else {
|
|
NI->ResourceSet = RSOther;
|
|
NI->Latency = 0;
|
|
}
|
|
}
|
|
|
|
// Add one slot for the instruction itself
|
|
NI->Latency++;
|
|
|
|
// Sum up all the latencies for max tally size
|
|
NSlots += NI->Latency;
|
|
}
|
|
}
|
|
|
|
/// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
|
|
///
|
|
void SimpleSched::PrepareNodeInfo() {
|
|
// Allocate node information
|
|
Info = new NodeInfo[NodeCount];
|
|
// Get base of all nodes table
|
|
SelectionDAG::allnodes_iterator AllNodes = DAG.allnodes_begin();
|
|
|
|
// For each node being scheduled
|
|
for (unsigned i = 0, N = NodeCount; i < N; i++) {
|
|
// Get next node from DAG all nodes table
|
|
SDNode *Node = AllNodes[i];
|
|
// Fast reference to node schedule info
|
|
NodeInfo* NI = &Info[i];
|
|
// Set up map
|
|
Map[Node] = NI;
|
|
// Set node
|
|
NI->Node = Node;
|
|
// Set pending visit count
|
|
NI->setPending(Node->use_size());
|
|
}
|
|
}
|
|
|
|
/// isStrongDependency - Return true if node A has results used by node B.
|
|
/// I.E., B must wait for latency of A.
|
|
bool SimpleSched::isStrongDependency(NodeInfo *A, NodeInfo *B) {
|
|
// If A defines for B then it's a strong dependency
|
|
return isDefiner(A, B);
|
|
}
|
|
|
|
/// isWeakDependency Return true if node A produces a result that will
|
|
/// conflict with operands of B.
|
|
bool SimpleSched::isWeakDependency(NodeInfo *A, NodeInfo *B) {
|
|
// TODO check for conflicting real registers and aliases
|
|
#if 0 // FIXME - Since we are in SSA form and not checking register aliasing
|
|
return A->Node->getOpcode() == ISD::EntryToken || isStrongDependency(B, A);
|
|
#else
|
|
return A->Node->getOpcode() == ISD::EntryToken;
|
|
#endif
|
|
}
|
|
|
|
/// ScheduleBackward - Schedule instructions so that any long latency
|
|
/// instructions and the critical path get pushed back in time. Time is run in
|
|
/// reverse to allow code reuse of the Tally and eliminate the overhead of
|
|
/// biasing every slot indices against NSlots.
|
|
void SimpleSched::ScheduleBackward() {
|
|
// Size and clear the resource tally
|
|
Tally.Initialize(NSlots);
|
|
// Get number of nodes to schedule
|
|
unsigned N = Ordering.size();
|
|
|
|
// For each node being scheduled
|
|
for (unsigned i = N; 0 < i--;) {
|
|
NodeInfo *NI = Ordering[i];
|
|
// Track insertion
|
|
unsigned Slot = NotFound;
|
|
|
|
// Compare against those previously scheduled nodes
|
|
unsigned j = i + 1;
|
|
for (; j < N; j++) {
|
|
// Get following instruction
|
|
NodeInfo *Other = Ordering[j];
|
|
|
|
// Check dependency against previously inserted nodes
|
|
if (isStrongDependency(NI, Other)) {
|
|
Slot = Other->Slot + Other->Latency;
|
|
break;
|
|
} else if (isWeakDependency(NI, Other)) {
|
|
Slot = Other->Slot;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If independent of others (or first entry)
|
|
if (Slot == NotFound) Slot = 0;
|
|
|
|
// Find a slot where the needed resources are available
|
|
if (NI->ResourceSet)
|
|
Slot = Tally.FindAndReserve(Slot, NI->Latency, NI->ResourceSet);
|
|
|
|
// Set node slot
|
|
NI->Slot = Slot;
|
|
|
|
// Insert sort based on slot
|
|
j = i + 1;
|
|
for (; j < N; j++) {
|
|
// Get following instruction
|
|
NodeInfo *Other = Ordering[j];
|
|
// Should we look further
|
|
if (Slot >= Other->Slot) break;
|
|
// Shuffle other into ordering
|
|
Ordering[j - 1] = Other;
|
|
}
|
|
// Insert node in proper slot
|
|
if (j != i + 1) Ordering[j - 1] = NI;
|
|
}
|
|
}
|
|
|
|
/// ScheduleForward - Schedule instructions to maximize packing.
|
|
///
|
|
void SimpleSched::ScheduleForward() {
|
|
// Size and clear the resource tally
|
|
Tally.Initialize(NSlots);
|
|
// Get number of nodes to schedule
|
|
unsigned N = Ordering.size();
|
|
|
|
// For each node being scheduled
|
|
for (unsigned i = 0; i < N; i++) {
|
|
NodeInfo *NI = Ordering[i];
|
|
// Track insertion
|
|
unsigned Slot = NotFound;
|
|
|
|
// Compare against those previously scheduled nodes
|
|
unsigned j = i;
|
|
for (; 0 < j--;) {
|
|
// Get following instruction
|
|
NodeInfo *Other = Ordering[j];
|
|
|
|
// Check dependency against previously inserted nodes
|
|
if (isStrongDependency(Other, NI)) {
|
|
Slot = Other->Slot + Other->Latency;
|
|
break;
|
|
} else if (isWeakDependency(Other, NI)) {
|
|
Slot = Other->Slot;
|
|
break;
|
|
}
|
|
}
|
|
|
|
// If independent of others (or first entry)
|
|
if (Slot == NotFound) Slot = 0;
|
|
|
|
// Find a slot where the needed resources are available
|
|
if (NI->ResourceSet)
|
|
Slot = Tally.FindAndReserve(Slot, NI->Latency, NI->ResourceSet);
|
|
|
|
// Set node slot
|
|
NI->Slot = Slot;
|
|
|
|
// Insert sort based on slot
|
|
j = i;
|
|
for (; 0 < j--;) {
|
|
// Get following instruction
|
|
NodeInfo *Other = Ordering[j];
|
|
// Should we look further
|
|
if (Slot >= Other->Slot) break;
|
|
// Shuffle other into ordering
|
|
Ordering[j + 1] = Other;
|
|
}
|
|
// Insert node in proper slot
|
|
if (j != i) Ordering[j + 1] = NI;
|
|
}
|
|
}
|
|
|
|
/// EmitAll - Emit all nodes in schedule sorted order.
|
|
///
|
|
void SimpleSched::EmitAll() {
|
|
// For each node in the ordering
|
|
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
|
|
// Get the scheduling info
|
|
NodeInfo *NI = Ordering[i];
|
|
#if 0
|
|
// Iterate through nodes
|
|
NodeGroupIterator NGI(Ordering[i]);
|
|
while (NodeInfo *NI = NGI.next()) EmitNode(NI);
|
|
#else
|
|
if (NI->isInGroup()) {
|
|
if (NI->isGroupLeader()) {
|
|
NodeGroupIterator NGI(Ordering[i]);
|
|
while (NodeInfo *NI = NGI.next()) EmitNode(NI);
|
|
}
|
|
} else {
|
|
EmitNode(NI);
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
|
|
/// CountResults - The results of target nodes have register or immediate
|
|
/// operands first, then an optional chain, and optional flag operands (which do
|
|
/// not go into the machine instrs.)
|
|
unsigned SimpleSched::CountResults(SDNode *Node) {
|
|
unsigned N = Node->getNumValues();
|
|
while (N && Node->getValueType(N - 1) == MVT::Flag)
|
|
--N;
|
|
if (N && Node->getValueType(N - 1) == MVT::Other)
|
|
--N; // Skip over chain result.
|
|
return N;
|
|
}
|
|
|
|
/// CountOperands The inputs to target nodes have any actual inputs first,
|
|
/// followed by an optional chain operand, then flag operands. Compute the
|
|
/// number of actual operands that will go into the machine instr.
|
|
unsigned SimpleSched::CountOperands(SDNode *Node) {
|
|
unsigned N = Node->getNumOperands();
|
|
while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
|
|
--N;
|
|
if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
|
|
--N; // Ignore chain if it exists.
|
|
return N;
|
|
}
|
|
|
|
/// CreateVirtualRegisters - Add result register values for things that are
|
|
/// defined by this instruction.
|
|
unsigned SimpleSched::CreateVirtualRegisters(MachineInstr *MI,
|
|
unsigned NumResults,
|
|
const TargetInstrDescriptor &II) {
|
|
// Create the result registers for this node and add the result regs to
|
|
// the machine instruction.
|
|
const TargetOperandInfo *OpInfo = II.OpInfo;
|
|
unsigned ResultReg = RegMap->createVirtualRegister(OpInfo[0].RegClass);
|
|
MI->addRegOperand(ResultReg, MachineOperand::Def);
|
|
for (unsigned i = 1; i != NumResults; ++i) {
|
|
assert(OpInfo[i].RegClass && "Isn't a register operand!");
|
|
MI->addRegOperand(RegMap->createVirtualRegister(OpInfo[i].RegClass),
|
|
MachineOperand::Def);
|
|
}
|
|
return ResultReg;
|
|
}
|
|
|
|
/// EmitNode - Generate machine code for an node and needed dependencies.
|
|
///
|
|
void SimpleSched::EmitNode(NodeInfo *NI) {
|
|
unsigned VRBase = 0; // First virtual register for node
|
|
SDNode *Node = NI->Node;
|
|
|
|
// If machine instruction
|
|
if (Node->isTargetOpcode()) {
|
|
unsigned Opc = Node->getTargetOpcode();
|
|
const TargetInstrDescriptor &II = TII.get(Opc);
|
|
|
|
unsigned NumResults = CountResults(Node);
|
|
unsigned NodeOperands = CountOperands(Node);
|
|
unsigned NumMIOperands = NodeOperands + NumResults;
|
|
#ifndef NDEBUG
|
|
assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
|
|
"#operands for dag node doesn't match .td file!");
|
|
#endif
|
|
|
|
// Create the new machine instruction.
|
|
MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
|
|
|
|
// Add result register values for things that are defined by this
|
|
// instruction.
|
|
if (NumResults) VRBase = CreateVirtualRegisters(MI, NumResults, II);
|
|
|
|
// Emit all of the actual operands of this instruction, adding them to the
|
|
// instruction as appropriate.
|
|
for (unsigned i = 0; i != NodeOperands; ++i) {
|
|
if (Node->getOperand(i).isTargetOpcode()) {
|
|
// Note that this case is redundant with the final else block, but we
|
|
// include it because it is the most common and it makes the logic
|
|
// simpler here.
|
|
assert(Node->getOperand(i).getValueType() != MVT::Other &&
|
|
Node->getOperand(i).getValueType() != MVT::Flag &&
|
|
"Chain and flag operands should occur at end of operand list!");
|
|
|
|
// Get/emit the operand.
|
|
unsigned VReg = getVR(Node->getOperand(i));
|
|
MI->addRegOperand(VReg, MachineOperand::Use);
|
|
|
|
// Verify that it is right.
|
|
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
|
|
assert(II.OpInfo[i+NumResults].RegClass &&
|
|
"Don't have operand info for this instruction!");
|
|
assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
|
|
"Register class of operand and regclass of use don't agree!");
|
|
} else if (ConstantSDNode *C =
|
|
dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
|
|
MI->addZeroExtImm64Operand(C->getValue());
|
|
} else if (RegisterSDNode*R =
|
|
dyn_cast<RegisterSDNode>(Node->getOperand(i))) {
|
|
MI->addRegOperand(R->getReg(), MachineOperand::Use);
|
|
} else if (GlobalAddressSDNode *TGA =
|
|
dyn_cast<GlobalAddressSDNode>(Node->getOperand(i))) {
|
|
MI->addGlobalAddressOperand(TGA->getGlobal(), false, 0);
|
|
} else if (BasicBlockSDNode *BB =
|
|
dyn_cast<BasicBlockSDNode>(Node->getOperand(i))) {
|
|
MI->addMachineBasicBlockOperand(BB->getBasicBlock());
|
|
} else if (FrameIndexSDNode *FI =
|
|
dyn_cast<FrameIndexSDNode>(Node->getOperand(i))) {
|
|
MI->addFrameIndexOperand(FI->getIndex());
|
|
} else if (ConstantPoolSDNode *CP =
|
|
dyn_cast<ConstantPoolSDNode>(Node->getOperand(i))) {
|
|
unsigned Idx = ConstPool->getConstantPoolIndex(CP->get());
|
|
MI->addConstantPoolIndexOperand(Idx);
|
|
} else if (ExternalSymbolSDNode *ES =
|
|
dyn_cast<ExternalSymbolSDNode>(Node->getOperand(i))) {
|
|
MI->addExternalSymbolOperand(ES->getSymbol(), false);
|
|
} else {
|
|
assert(Node->getOperand(i).getValueType() != MVT::Other &&
|
|
Node->getOperand(i).getValueType() != MVT::Flag &&
|
|
"Chain and flag operands should occur at end of operand list!");
|
|
unsigned VReg = getVR(Node->getOperand(i));
|
|
MI->addRegOperand(VReg, MachineOperand::Use);
|
|
|
|
// Verify that it is right.
|
|
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
|
|
assert(II.OpInfo[i+NumResults].RegClass &&
|
|
"Don't have operand info for this instruction!");
|
|
assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
|
|
"Register class of operand and regclass of use don't agree!");
|
|
}
|
|
}
|
|
|
|
// Now that we have emitted all operands, emit this instruction itself.
|
|
if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
|
|
BB->insert(BB->end(), MI);
|
|
} else {
|
|
// Insert this instruction into the end of the basic block, potentially
|
|
// taking some custom action.
|
|
BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
|
|
}
|
|
} else {
|
|
switch (Node->getOpcode()) {
|
|
default:
|
|
Node->dump();
|
|
assert(0 && "This target-independent node should have been selected!");
|
|
case ISD::EntryToken: // fall thru
|
|
case ISD::TokenFactor:
|
|
break;
|
|
case ISD::CopyToReg: {
|
|
unsigned Val = getVR(Node->getOperand(2));
|
|
MRI.copyRegToReg(*BB, BB->end(),
|
|
cast<RegisterSDNode>(Node->getOperand(1))->getReg(), Val,
|
|
RegMap->getRegClass(Val));
|
|
break;
|
|
}
|
|
case ISD::CopyFromReg: {
|
|
unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
|
|
|
|
// Figure out the register class to create for the destreg.
|
|
const TargetRegisterClass *TRC = 0;
|
|
if (MRegisterInfo::isVirtualRegister(SrcReg)) {
|
|
TRC = RegMap->getRegClass(SrcReg);
|
|
} else {
|
|
// Pick the register class of the right type that contains this physreg.
|
|
for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
|
|
E = MRI.regclass_end(); I != E; ++I)
|
|
if ((*I)->getType() == Node->getValueType(0) &&
|
|
(*I)->contains(SrcReg)) {
|
|
TRC = *I;
|
|
break;
|
|
}
|
|
assert(TRC && "Couldn't find register class for reg copy!");
|
|
}
|
|
|
|
// Create the reg, emit the copy.
|
|
VRBase = RegMap->createVirtualRegister(TRC);
|
|
MRI.copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
assert(NI->VRBase == 0 && "Node emitted out of order - early");
|
|
NI->VRBase = VRBase;
|
|
}
|
|
|
|
/// Schedule - Order nodes according to selected style.
|
|
///
|
|
void SimpleSched::Schedule() {
|
|
// Number the nodes
|
|
NodeCount = DAG.allnodes_size();
|
|
// Set up minimum info for scheduling.
|
|
PrepareNodeInfo();
|
|
// Construct node groups for flagged nodes
|
|
IdentifyGroups();
|
|
// Breadth first walk of DAG
|
|
VisitAll();
|
|
|
|
// Don't waste time if is only entry and return
|
|
if (ScheduleStyle != noScheduling && NodeCount > 3) {
|
|
// Get latency and resource requirements
|
|
GatherSchedulingInfo();
|
|
DEBUG(dump("Pre-"));
|
|
// Push back long instructions and critical path
|
|
ScheduleBackward();
|
|
DEBUG(dump("Mid-"));
|
|
// Pack instructions to maximize resource utilization
|
|
ScheduleForward();
|
|
}
|
|
|
|
DEBUG(dump("Post-"));
|
|
// Emit in scheduled order
|
|
EmitAll();
|
|
}
|
|
|
|
/// printSI - Print schedule info.
|
|
///
|
|
void SimpleSched::printSI(std::ostream &O, NodeInfo *NI) const {
|
|
#ifndef NDEBUG
|
|
using namespace std;
|
|
SDNode *Node = NI->Node;
|
|
O << " "
|
|
<< hex << Node
|
|
<< ", RS=" << NI->ResourceSet
|
|
<< ", Lat=" << NI->Latency
|
|
<< ", Slot=" << NI->Slot
|
|
<< ", ARITY=(" << Node->getNumOperands() << ","
|
|
<< Node->getNumValues() << ")"
|
|
<< " " << Node->getOperationName(&DAG);
|
|
if (isFlagDefiner(Node)) O << "<#";
|
|
if (isFlagUser(Node)) O << ">#";
|
|
#endif
|
|
}
|
|
|
|
/// print - Print ordering to specified output stream.
|
|
///
|
|
void SimpleSched::print(std::ostream &O) const {
|
|
#ifndef NDEBUG
|
|
using namespace std;
|
|
O << "Ordering\n";
|
|
for (unsigned i = 0, N = Ordering.size(); i < N; i++) {
|
|
NodeInfo *NI = Ordering[i];
|
|
printSI(O, NI);
|
|
O << "\n";
|
|
if (NI->isGroupLeader()) {
|
|
NodeGroup *Group = NI->Group;
|
|
for (NIIterator NII = Group->begin(), E = Group->end();
|
|
NII != E; NII++) {
|
|
O << " ";
|
|
printSI(O, *NII);
|
|
O << "\n";
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/// dump - Print ordering to std::cerr.
|
|
///
|
|
void SimpleSched::dump() const {
|
|
print(std::cerr);
|
|
}
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
/// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
|
|
/// target node in the graph.
|
|
void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &SD) {
|
|
if (ViewDAGs) SD.viewGraph();
|
|
BB = SimpleSched(SD, BB).Run();
|
|
}
|