Evan Cheng 0a942dbb1e Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. ... The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that. Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-19 01:08:17 +00:00
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CodeGen	Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.	2010-05-19 01:08:17 +00:00
DebugInfo	Enable multiple Compile Units in one module.	2010-05-10 22:49:55 +00:00
ExecutionEngine
Feature	fix PR7105 by enumerating MDNodes on all @llvm.foo	2010-05-10 20:53:17 +00:00
FrontendAda
FrontendC	Add a test to make sure that we're lowering the shift amount correctly.	2010-05-19 00:22:04 +00:00
FrontendC++	Test case for r103633.	2010-05-12 18:31:04 +00:00
FrontendFortran
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LLVMC
MC	Quick test to make sure we're emitting the tbss section correctly.	2010-05-18 21:40:20 +00:00
Other	XFAIL the test I added with vg_leak, apparently it is the first and only llc	2010-05-14 07:47:51 +00:00
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Transforms	Actually run the test. Thanks Daniel Dunbar!	2010-05-13 17:41:06 +00:00
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